Commit 453740de authored Sep 07, 2017 by Chris Wilson Committed by Greg Kroah-Hartman Sep 26, 2018

drm/i915: Apply the GTT write flush for all !llc machines

commit c5ba5b24 upstream.

We also see the delayed GTT write issue on i915g/i915gm, so let's
presume that it is a universal problem for all !llc machines, and that we
just haven't yet noticed on g33, gen4 and gen5 machines.

v2: Use a register that exists on all platforms

Testcase: igt/gem_mmap_gtt/coherency # i915gm
References: https://bugs.freedesktop.org/show_bug.cgi?id=102577


Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907184520.5032-1-chris@chris-wilson.co.uk


Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 425026ae

drivers/gpu/drm/i915/i915_gem.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -687,10 +687,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)

	switch (obj->base.write_domain) {		switch (obj->base.write_domain) {
	case I915_GEM_DOMAIN_GTT:		case I915_GEM_DOMAIN_GTT:
	if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {		if (!HAS_LLC(dev_priv)) {
	intel_runtime_pm_get(dev_priv);		intel_runtime_pm_get(dev_priv);
	spin_lock_irq(&dev_priv->uncore.lock);		spin_lock_irq(&dev_priv->uncore.lock);
	POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));		POSTING_READ_FW(RING_HEAD(dev_priv->engine[RCS]->mmio_base));
	spin_unlock_irq(&dev_priv->uncore.lock);		spin_unlock_irq(&dev_priv->uncore.lock);
	intel_runtime_pm_put(dev_priv);		intel_runtime_pm_put(dev_priv);
	}		}