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Commit 44b83b32 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-rockchip' into next

* pci/host-rockchip:
  PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init()
  PCI: rockchip: Split out rockchip_cfg_atu()
  PCI: rockchip: Clean up bit definitions for PCIE_RC_CONFIG_LCS
  PCI: rockchip: Correct the use of FTS mask
  PCI: rockchip: Remove the pointer to L1 substate cap
  PCI: rockchip: Specify the link capability
  PCI: rockchip: Fix negotiated lanes calculation
  PCI: rockchip: Add Kconfig COMPILE_TEST
  PCI: rockchip: Mark RC as common clock architecture
  PCI: rockchip: Provide captured slot power limit and scale
  PCI: rockchip: Add three new resets as required properties
  PCI: Don't attempt to claim shadow copies of ROM
  PCI: designware: Check for iATU unroll support after initializing host
  PCI: qcom: Fix pp->dev usage before assignment
  PCI: designware-plat: Update author email address
  PCI: layerscape: Fix drvdata usage before assignment
  PCI: designware-plat: Change maintainer to Jose Abreu
parents a1d9190d 0722bdd2
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+8 −3
Original line number Diff line number Diff line
@@ -26,13 +26,16 @@ Required properties:
	- "sys"
	- "legacy"
	- "client"
- resets: Must contain five entries for each entry in reset-names.
- resets: Must contain seven entries for each entry in reset-names.
	   See ../reset/reset.txt for details.
- reset-names: Must include the following names
	- "core"
	- "mgmt"
	- "mgmt-sticky"
	- "pipe"
	- "pm"
	- "aclk"
	- "pclk"
- pinctrl-names : The pin control state names
- pinctrl-0: The "default" pinctrl state
- #interrupt-cells: specifies the number of cells needed to encode an
@@ -86,8 +89,10 @@ pcie0: pcie@f8000000 {
	reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
	reg-names = "axi-base", "apb-base";
	resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
	reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
		 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
		      "pm", "pclk", "aclk";
	phys = <&pcie_phy>;
	phy-names = "pcie-phy";
	pinctrl-names = "default";
+1 −1
Original line number Diff line number Diff line
@@ -9300,7 +9300,7 @@ S: Maintained
F:	drivers/pci/host/*designware*

PCI DRIVER FOR SYNOPSYS PROTOTYPING DEVICE
M:	Joao Pinto <jpinto@synopsys.com>
M:	Jose Abreu <Jose.Abreu@synopsys.com>
L:	linux-pci@vger.kernel.org
S:	Maintained
F:	Documentation/devicetree/bindings/pci/designware-pcie.txt
+1 −1
Original line number Diff line number Diff line
@@ -278,7 +278,7 @@ config PCIE_ARTPEC6

config PCIE_ROCKCHIP
	bool "Rockchip PCIe controller"
	depends on ARCH_ROCKCHIP
	depends on ARCH_ROCKCHIP || COMPILE_TEST
	depends on OF
	depends on PCI_MSI_IRQ_DOMAIN
	select MFD_SYSCON
+1 −1
Original line number Diff line number Diff line
@@ -255,6 +255,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev)

	pp = &pcie->pp;
	pp->dev = dev;
	pcie->drvdata = match->data;
	pp->ops = pcie->drvdata->ops;

	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
@@ -262,7 +263,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
	if (IS_ERR(pcie->pp.dbi_base))
		return PTR_ERR(pcie->pp.dbi_base);

	pcie->drvdata = match->data;
	pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;

	if (!ls_pcie_is_bridge(pcie))
+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@
 *
 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
 *
 * Authors: Joao Pinto <jpinto@synopsys.com>
 * Authors: Joao Pinto <jpmpinto@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
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