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Commit 43994d82 authored by Dave Martin's avatar Dave Martin Committed by Will Deacon
Browse files

arm64/sve: Detect SVE and activate runtime support 



This patch enables detection of hardware SVE support via the
cpufeatures framework, and reports its presence to the kernel and
userspace via the new ARM64_SVE cpucap and HWCAP_SVE hwcap
respectively.

Userspace can also detect SVE using ID_AA64PFR0_EL1, using the
cpufeatures MRS emulation.

When running on hardware that supports SVE, this enables runtime
kernel support for SVE, and allows user tasks to execute SVE
instructions and make of the of the SVE-specific user/kernel
interface extensions implemented by this series.

Signed-off-by: default avatarDave Martin <Dave.Martin@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 07d79fe7

Documentation/arm64/cpu-feature-registers.txt

+5 −1
Original line number Diff line number Diff line
@@ -142,7 +142,11 @@ infrastructure: 
     x--------------------------------------------------x

     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | RES0                         | [63-28] |    n    |

     | RES0                         | [63-36] |    n    |

     |--------------------------------------------------|

     | SVE                          | [35-32] |    y    |

     |--------------------------------------------------|

     | RES0                         | [31-28] |    n    |

     |--------------------------------------------------|

     | GIC                          | [27-24] |    n    |

     |--------------------------------------------------|

Documentation/arm64/elf_hwcaps.txt

+4 −0
Original line number Diff line number Diff line
@@ -154,3 +154,7 @@ HWCAP_ASIMDDP 
HWCAP_SHA512



    Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0002.



HWCAP_SVE



    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -40,7 +40,8 @@ 
#define ARM64_WORKAROUND_858921			19

#define ARM64_WORKAROUND_CAVIUM_30115		20

#define ARM64_HAS_DCPOP				21

#define ARM64_SVE				22



#define ARM64_NCAPS				22

#define ARM64_NCAPS				23



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/cpufeature.h

+2 −1
Original line number Diff line number Diff line
@@ -273,7 +273,8 @@ static inline bool system_uses_ttbr0_pan(void) 


static inline bool system_supports_sve(void)

{

	return false;

	return IS_ENABLED(CONFIG_ARM64_SVE) &&

		cpus_have_const_cap(ARM64_SVE);

}



/*

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -41,5 +41,6 @@ 
#define HWCAP_SM4		(1 << 19)

#define HWCAP_ASIMDDP		(1 << 20)

#define HWCAP_SHA512		(1 << 21)

#define HWCAP_SVE		(1 << 22)



#endif /* _UAPI__ASM_HWCAP_H */