clk: qcom: Update mdss_ahb_clk clock divider for SM6150

RCG divider of disp_cc_mdss_ahb_clk clock is required to
be updated to generate 37.5MHz and 75MHz frequencies, so
update the same on SM6150.
Also keep the gpll0_main clock source enabled by default as
it is required for generating 37.5MHz and 75MHz frequencies.

Change-Id: I07db5e6ec96c5cb13df96209041e79bfb2c0e450
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>