Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 42b32953 authored by Arun Prakash's avatar Arun Prakash
Browse files

ARM: dts: msm: Add UFS support for kdump kernel on sa8155 



Add UFS support for kdump kernel on sa8155.

Change-Id: I6bfe75b8474077c28d79cf65979d5e39c2072a02
Signed-off-by: default avatarArun Prakash <app@codeaurora.org>
parent 96a9e10b

arch/arm64/boot/dts/qcom/sa8155-capture.dtsi

+176 −0
Original line number Diff line number Diff line
@@ -345,6 +345,178 @@ 
			<MSM_BUS_SLAVE_IMEM_CFG>,

			<0 1000>;

	};



	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

				"iface_clk", "ice_core_clk";

		clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_phy_gdsc>;

		qcom,msm-bus,name = "ufs_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<1 650 0 0>,    /* No vote */

				<1 650 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

		compatible = "qcom,ufs-phy-qmp-v4";

		reg = <0x1d87000 0xda8>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <2>;



		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;



		vdda-pll-supply = <&pm8150_2_l8>;

		vdda-phy-max-microamp = <87100>;

		vdda-pll-max-microamp = <18300>;

		vdda-phy-supply = <&pm8150_1_l5>;



		status = "ok";

	};



	ufshc_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x2500>;

		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */



		clock-names =

			"core_clk",

			"bus_aggr_clk",

			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

		clocks =

			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

		freq-table-hz =

			<37500000 300000000>,

			<0 0>,

			<0 0>,

			<37500000 300000000>,

			<37500000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_mem";

		qcom,msm-bus,num-cases = <26>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		/*

		 * During HS G3 UFS runs at nominal voltage corner, vote

		 * higher bandwidth to push other buses in the data path

		 * to run at nominal to achieve max throughput.

		 * 4GBps pushes BIMC to run at nominal.

		 * 200MBps pushes CNOC to run at nominal.

		 * Vote for half of this bandwidth for HS G3 1-lane.

		 * For max bandwidth, vote high enough to push the buses

		 * to run in turbo voltage corner.

		 */

		<123 512 0 0>, <1 757 0 0>,          /* No vote */

		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G1 L2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G2 L2 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G3 L2 */

		<123 512 14752 0>, <1 757 1000 0>,   /* PWM G4 L2 */

		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */

		<123 512 4194304 0>, <1 757 204800 0>,  /* HS G4 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */

		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */

		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */

		<123 512 8388608 0>, <1 757 409600 0>, /* HS G4 RA L2 */

		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */

		<123 512 4194304 0>, <1 757 204800 0>,  /* HS G4 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */

		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */

		/* As UFS working in HS G3 RB L2 mode, aggregated

		 * bandwidth (AB) should take care of providing

		 * optimum throughput requested. However, as tested,

		 * in order to scale up CNOC clock, instantaneous

		 * bindwidth (IB) needs to be given a proper value too.

		 */

		<123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */

		<123 512 8388608 0>, <1 757 409600 409600>, /* HS G4 RB L2 */

		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */



		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",

		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",

		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",

		"MAX";



		/* PM QoS */

		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-cpu-group-latency-us = <44 44>;

		qcom,pm-qos-default-cpu = <0>;



		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";

		pinctrl-0 = <&ufs_dev_reset_assert>;

		pinctrl-1 = <&ufs_dev_reset_deassert>;



		resets = <&clock_gcc GCC_UFS_PHY_BCR>;

		reset-names = "core_reset";



		vdd-hba-supply = <&ufs_phy_gdsc>;

		vdd-hba-fixed-regulator;

		vcc-supply = <&pm8150_1_l10>;

		vcc-voltage-level = <2950000 2960000>;

		vccq2-supply = <&pm8150_1_s4>;

		vcc-max-microamp = <750000>;

		vccq2-max-microamp = <750000>;



		qcom,vddp-ref-clk-supply = <&pm8150_2_l5>;

		qcom,vddp-ref-clk-max-microamp = <100>;



		status = "ok";

	};



};



&apps_smmu {
@@ -362,6 +534,10 @@ 
		<0x1084 0x1 0x303>;

};



&ufs_phy_gdsc {

	status = "ok";

};



#include "sa8155-regulator.dtsi"

#include "sm8150-pinctrl.dtsi"

#include "sm8150-bus.dtsi"