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Commit 4234fa74 authored by Mitul Golani's avatar Mitul Golani
Browse files

serial: msm_geni_serial: Double clock-divider for kona based hw 



Clock devider needs to get double for kona based
HW as sampling rate is half.

Change-Id: I7a5d2deeb36df918c009afe871e82c27cdb74e0b
Signed-off-by: default avatarMitul Golani <mgolani@codeaurora.org>
parent 3091c721

drivers/platform/msm/qcom-geni-se.c

+0 −3
Original line number Diff line number Diff line
@@ -127,9 +127,6 @@ struct geni_se_device { 
	bool vote_for_bw;

};



/* Offset of QUPV3 Hardware Version Register */

#define QUPV3_HW_VER (0x4)



#define HW_VER_MAJOR_MASK GENMASK(31, 28)

#define HW_VER_MAJOR_SHFT 28

#define HW_VER_MINOR_MASK GENMASK(27, 16)

drivers/tty/serial/msm_geni_serial.c

+12 −0
Original line number Diff line number Diff line
@@ -131,6 +131,8 @@ 


#define DMA_RX_BUF_SIZE		(2048)

#define UART_CONSOLE_RX_WM	(2)

#define QUP_VER			(0x20050000)



struct msm_geni_serial_port {

	struct uart_port uport;

	char name[20];
@@ -199,6 +201,11 @@ static atomic_t uart_line_id = ATOMIC_INIT(0); 
static struct msm_geni_serial_port msm_geni_console_port;

static struct msm_geni_serial_port msm_geni_serial_ports[GENI_UART_NR_PORTS];



static int hw_version_info(void __iomem *base_addr)

{

	return geni_read_reg(base_addr, QUPV3_HW_VER);

}



static void msm_geni_serial_config_port(struct uart_port *uport, int cfg_flags)

{

	if (cfg_flags & UART_CONFIG_TYPE)
@@ -1792,6 +1799,7 @@ static void geni_serial_write_term_regs(struct uart_port *uport, u32 loopback, 
						SE_UART_TX_STOP_BIT_LEN);

	geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);

}



static int get_clk_div_rate(unsigned int baud, unsigned long *desired_clk_rate)
@@ -1855,6 +1863,8 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, 
	if (clk_div <= 0)

		goto exit_set_termios;



	if (hw_version_info(uport->membase) >= QUP_VER)

		clk_div *= 2;

	uport->uartclk = clk_rate;

	clk_set_rate(port->serial_rsc.se_clk, clk_rate);

	ser_clk_cfg |= SER_CLK_EN;
@@ -2133,6 +2143,8 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, 
		goto exit_geni_serial_earlyconsetup;

	}



	if (hw_version_info(uport->membase) >= QUP_VER)

		clk_div *= 2;

	s_clk_cfg |= SER_CLK_EN;

	s_clk_cfg |= (clk_div << CLK_DIV_SHFT);

include/linux/qcom-geni-se.h

+1 −0
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ struct se_geni_rsc { 
#define SE_DMA_DEBUG_REG0		(0xE40)

#define SLAVE_MODE_EN			(BIT(3))

#define START_TRIGGER			(BIT(0))

#define QUPV3_HW_VER			(0x4)



/* GENI_OUTPUT_CTRL fields */

#define DEFAULT_IO_OUTPUT_CTRL_MSK	(GENMASK(6, 0))