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Commit 422bd2c9 authored by Fuad Hossain's avatar Fuad Hossain
Browse files

drm/msm/sde: add pending retire fence count to event logs 



Add the pending retire fence count to the event logs. This
will make it easier to track sde fence signalling issues
in the future.

Change-Id: Ib6e5e45f524f4cd7e32b7e2b529b086a511e0b80
Signed-off-by: default avatarFuad Hossain <fhossain@codeaurora.org>
parent 3ef19c0b

drivers/gpu/drm/msm/sde/sde_encoder.c

+7 −2
Original line number Diff line number Diff line
@@ -3329,6 +3329,7 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc, 
	struct sde_hw_ctl *ctl;

	unsigned long lock_flags;

	struct sde_encoder_virt *sde_enc;

	int pend_ret_fence_cnt;



	if (!drm_enc || !phys) {

		SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
@@ -3363,6 +3364,8 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc, 
	if (phys->ops.is_master && phys->ops.is_master(phys))

		atomic_inc(&phys->pending_retire_fence_cnt);



	pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);



	if ((extra_flush && extra_flush->pending_flush_mask)

			&& ctl->ops.update_pending_flush)

		ctl->ops.update_pending_flush(ctl, extra_flush);
@@ -3377,10 +3380,12 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc, 
		ctl->ops.get_pending_flush(ctl, &pending_flush);

		SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,

				ctl->idx - CTL_0,

				pending_flush.pending_flush_mask);

				pending_flush.pending_flush_mask,

				pend_ret_fence_cnt);

	} else {

		SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,

				ctl->idx - CTL_0);

				ctl->idx - CTL_0,

				pend_ret_fence_cnt);

	}

}

drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c

+8 −1
Original line number Diff line number Diff line
@@ -493,6 +493,7 @@ static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) 
	u32 reset_status = 0;

	int new_cnt = -1, old_cnt = -1;

	u32 event = 0;

	int pend_ret_fence_cnt;



	if (!phys_enc)

		return;
@@ -519,6 +520,7 @@ static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) 
		goto not_flushed;



	new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);

	pend_ret_fence_cnt = atomic_read(&phys_enc->pending_retire_fence_cnt);



	/* signal only for master, where there is a pending kickoff */

	if (sde_encoder_phys_vid_is_master(phys_enc)) {
@@ -544,7 +546,8 @@ static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) 


	SDE_EVT32_IRQ(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0,

			old_cnt, new_cnt, reset_status ? SDE_EVTLOG_ERROR : 0,

			flush_register, event);

			flush_register, event,

			pend_ret_fence_cnt);



	/* Signal any waiting atomic commit thread */

	wake_up_all(&phys_enc->pending_kickoff_wq);
@@ -822,6 +825,8 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) 
skip_flush:

	SDE_DEBUG_VIDENC(vid_enc, "update pending flush ctl %d intf %d\n",

		ctl->idx - CTL_0, intf->idx);

	SDE_EVT32(DRMID(phys_enc->parent),

		atomic_read(&phys_enc->pending_retire_fence_cnt));



	/* ctl_flush & timing engine enable will be triggered by framework */

	if (phys_enc->enable_state == SDE_ENC_DISABLED)
@@ -1097,6 +1102,8 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) 
				phys_enc->hw_pp->merge_3d->idx);



exit:

	SDE_EVT32(DRMID(phys_enc->parent),

		atomic_read(&phys_enc->pending_retire_fence_cnt));

	phys_enc->vfp_cached = 0;

	phys_enc->enable_state = SDE_ENC_DISABLED;

}