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Commit 419ed294 authored by Karthik Anantha Ram's avatar Karthik Anantha Ram
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msm: camera: icp: Send only required core info as part of PC



As part of ipe_bps_pc only the core we want to put into collapse
mode needs to be notified to FW. SW does not need to send
consolidated core info to FW.

Change-Id: Idae162c22032a774885f212de74a2801ace55486
Signed-off-by: default avatarKarthik Anantha Ram <kartanan@codeaurora.org>
parent 2d526662
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+12 −18
Original line number Diff line number Diff line
@@ -1088,6 +1088,7 @@ static int cam_icp_mgr_ipe_bps_resume(struct cam_icp_hw_mgr *hw_mgr,
	struct cam_hw_intf *ipe0_dev_intf = NULL;
	struct cam_hw_intf *ipe1_dev_intf = NULL;
	struct cam_hw_intf *bps_dev_intf = NULL;
	uint32_t core_info_mask = 0;
	int rc = 0;

	ipe0_dev_intf = hw_mgr->ipe0_dev_intf;
@@ -1111,8 +1112,8 @@ static int cam_icp_mgr_ipe_bps_resume(struct cam_icp_hw_mgr *hw_mgr,
			bps_dev_intf->hw_ops.process_cmd(
				bps_dev_intf->hw_priv,
				CAM_ICP_BPS_CMD_POWER_RESUME, NULL, 0);
			hw_mgr->core_info = hw_mgr->core_info | ICP_PWR_CLP_BPS;
		}
		core_info_mask = ICP_PWR_CLP_BPS;
	} else {
		if (hw_mgr->ipe_ctxt_cnt++)
			goto end;
@@ -1139,19 +1140,20 @@ static int cam_icp_mgr_ipe_bps_resume(struct cam_icp_hw_mgr *hw_mgr,
			}
		}
		hw_mgr->ipe_clk_state = true;
		if (icp_hw_mgr.ipe_bps_pc_flag) {
			hw_mgr->core_info = hw_mgr->core_info |
				(ICP_PWR_CLP_IPE0 | ICP_PWR_CLP_IPE1);
		}

		if ((icp_hw_mgr.ipe1_enable) &&
			(ipe1_dev_intf))
			core_info_mask = (ICP_PWR_CLP_IPE0 |
				ICP_PWR_CLP_IPE1);
		else
			core_info_mask = ICP_PWR_CLP_IPE0;
	}

	CAM_DBG(CAM_ICP, "core_info %X",  hw_mgr->core_info);
	CAM_DBG(CAM_ICP, "core_info %X", core_info_mask);
	if (icp_hw_mgr.ipe_bps_pc_flag)
		rc = hfi_enable_ipe_bps_pc(true, hw_mgr->core_info);
	else if (icp_hw_mgr.icp_pc_flag)
		rc = hfi_enable_ipe_bps_pc(false, hw_mgr->core_info);
		rc = hfi_enable_ipe_bps_pc(true, core_info_mask);
	else
		rc = hfi_enable_ipe_bps_pc(false, hw_mgr->core_info);
		rc = hfi_enable_ipe_bps_pc(false, core_info_mask);
end:
	return rc;
}
@@ -1192,8 +1194,6 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr,
				bps_dev_intf->hw_priv,
				CAM_ICP_BPS_CMD_POWER_COLLAPSE,
				NULL, 0);
			hw_mgr->core_info =
				hw_mgr->core_info & (~ICP_PWR_CLP_BPS);
		}

		if (hw_mgr->bps_clk_state) {
@@ -1235,14 +1235,8 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr,
		}

		hw_mgr->ipe_clk_state = false;
		if (icp_hw_mgr.ipe_bps_pc_flag &&
			!atomic_read(&hw_mgr->recovery)) {
			hw_mgr->core_info = hw_mgr->core_info &
				(~(ICP_PWR_CLP_IPE0 | ICP_PWR_CLP_IPE1));
		}
	}

	CAM_DBG(CAM_ICP, "Exit: core_info = %x", hw_mgr->core_info);
end:
	return rc;
}
+0 −2
Original line number Diff line number Diff line
@@ -304,7 +304,6 @@ struct cam_icp_clk_info {
 * @ipe0_enable: Flag for IPE0
 * @ipe1_enable: Flag for IPE1
 * @bps_enable: Flag for BPS
 * @core_info: 32 bit value , tells IPE0/1 and BPS
 * @a5_dev_intf : Device interface for A5
 * @ipe0_dev_intf: Device interface for IPE0
 * @ipe1_dev_intf: Device interface for IPE1
@@ -354,7 +353,6 @@ struct cam_icp_hw_mgr {
	bool ipe0_enable;
	bool ipe1_enable;
	bool bps_enable;
	uint32_t core_info;
	struct cam_hw_intf *a5_dev_intf;
	struct cam_hw_intf *ipe0_dev_intf;
	struct cam_hw_intf *ipe1_dev_intf;