Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 40da75f6 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "arm: dts: msm: Update USB QMP UNI PHY settings for sm8150 v2"

parents 43801d26 77714897

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+113 −11
Original line number Diff line number Diff line
@@ -994,6 +994,7 @@ 
	     USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0

	     USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

	     USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0

	     USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0

	     USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0

	     USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0

	     USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
@@ -1014,19 +1015,17 @@ 
	     USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0

	     USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0

	     USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0

	     USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

	     USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0

	     USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0

	     USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0

	     USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0

	     USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0

	     USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x2 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

	     USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

	     USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0

	     USB3_DP_QSERDES_TXA_LANE_MODE_1 0xd5 0

	     USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

	     USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
@@ -1034,7 +1033,7 @@ 
	     USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0

	     USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0

	     USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0

	     USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04 0

	     USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0

	     USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2f 0

	     USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

	     USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xff 0
@@ -1054,7 +1053,6 @@ 
	     USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xc0 0

	     USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0

	     USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

	     USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

	     USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0

	     USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0e 0

	     USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xbf 0
@@ -1077,8 +1075,8 @@ 
	     USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0

	     USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0

	     USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0

	     USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x20 0

	     USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04 0

	     USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x01 0

	     USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0

	     USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2f 0

	     USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

	     USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xff 0
@@ -1098,7 +1096,6 @@ 
	     USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xc0 0

	     USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0

	     USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

	     USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

	     USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0

	     USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0e 0

	     USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xbf 0
@@ -1116,18 +1113,123 @@ 
	     USB3_DP_QSERDES_RXB_DCC_CTRL1 0xc 0

	     USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xd0 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x17 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0

	     USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0

	     USB3_DP_PCS_RX_SIGDET_LVL 0xaa 0

	     USB3_DP_PCS_CDR_RESET_TIME 0x0f 0

	     USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0

	     USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0

	     USB3_DP_PCS_EQ_CONFIG1 0x0d 0

	     USB3_DP_PCS_EQ_CONFIG5 0x50 0

	     USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0c 0

	     USB3_DP_PCS_EQ_CONFIG1 0x4b 0

	     USB3_DP_PCS_EQ_CONFIG5 0x10 0

	     USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0

	     USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

	     0xffffffff 0xffffffff 0x00>;

};



&usb_qmp_phy {

	qcom,qmp-phy-init-seq =

	    <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0

	     USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

	     USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0

	     USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0

	     USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0

	     USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0

	     USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0

	     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0

	     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0

	     USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0

	     USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0

	     USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0

	     USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0

	     USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0

	     USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0

	     USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0

	     USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0

	     USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0

	     USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0

	     USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0

	     USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0

	     USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0

	     USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0

	     USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0

	     USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0

	     USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0

	     USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0

	     USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0

	     USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0

	     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0

	     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0

	     USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0

	     USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0

	     USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0

	     USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0

	     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0

	     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

	     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0

	     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0

	     USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0

	     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xb8 0

	     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0

	     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0

	     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0

	     USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xef 0

	     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb3 0

	     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0

	     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0

	     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0

	     USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0

	     USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0

	     USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0

	     USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0

	     USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0

	     USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0

	     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0

	     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0

	     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0

	     USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

	     USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x08 0

	     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0

	     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0

	     USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0

	     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

	     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

	     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0

	     USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0

	     USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0

	     USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

	     USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0

	     USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0

	     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0

	     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0

	     USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0

	     USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0

	     USB3_UNI_QSERDES_RX_DCC_CTRL1 0xc 0

	     USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0

	     USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0

	     USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0

	     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x05 0

	     USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0

	     USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0

	     USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0

	     USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0

	     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0

	     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0

	     USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0

	     USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

	     USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0

	     USB3_UNI_PCS_CDR_RESET_TIME 0x0f 0

	     USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0

	     USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0

	     USB3_UNI_PCS_EQ_CONFIG1 0x4b 0

	     USB3_UNI_PCS_EQ_CONFIG5 0x10 0

	     USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0

	     USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0

	     0xffffffff 0xffffffff 0x00>;

};



/* qcedev override */

&qcom_cedev {

	qcom_cedev_ns_cb {

drivers/usb/phy/phy-msm-ssusb-qmp.c

+9 −16
Original line number Diff line number Diff line
@@ -83,12 +83,13 @@ enum core_ldo_levels { 
#define DP_MODE			BIT(1) /* enables DP mode */

#define USB3_DP_COMBO_MODE	(USB3_MODE | DP_MODE) /*enables combo mode */



/* USB3 Gen2 link training indicator */

/* PCS_STATUS2 link training indicator */

#define RX_EQUALIZATION_IN_PROGRESS	BIT(3)

#define USB3_DP_PCS_CDR_RESET_TIME	0x1DB0

#define USB3_UNI_PCS_CDR_RESET_TIME	0x09B0



/* PCS_CONFIG5 register offsets for Gen2 link training SW WA */

#define USB3_DP_PCS_EQ_CONFIG5		0x1DEC

#define USB3_UNI_PCS_EQ_CONFIG5		0x09EC

#define RXEQ_RETRAIN_MODE_SEL		BIT(6)



enum qmp_phy_rev_reg {

	USB3_PHY_PCS_STATUS,
@@ -156,7 +157,6 @@ struct msm_ssphy_qmp { 
	struct hrtimer		timer;



	bool			link_training_reset;

	u32			cdr_reset_time_offset;

	u32			eq_config5_offset;

};
@@ -461,7 +461,7 @@ static void usb_qmp_powerup_phy(struct msm_ssphy_qmp *phy) 


static void usb_qmp_apply_link_training_workarounds(struct msm_ssphy_qmp *phy)

{

	uint32_t version, major, minor;

	u32 version, major, minor, val;



	if (!phy->link_training_reset)

		return;
@@ -472,15 +472,12 @@ static void usb_qmp_apply_link_training_workarounds(struct msm_ssphy_qmp *phy) 


	/* sw workaround is needed only for hw reviosions below 2.1 */

	if ((major < 2) || (major == 2 && minor == 0)) {

		writel_relaxed(0x52, phy->base + phy->eq_config5_offset);

		val = readl_relaxed(phy->base + phy->eq_config5_offset);

		val |= RXEQ_RETRAIN_MODE_SEL;

		writel_relaxed(val, phy->base + phy->eq_config5_offset);

		phy->phy.link_training	= msm_ssphy_qmp_link_training;

		return;

	}



	if (!phy->cdr_reset_time_offset)

		return;



	writel_relaxed(0xA, phy->base + phy->cdr_reset_time_offset);

}



/* SSPHY Initialization */
@@ -1228,13 +1225,9 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev) 


	if (phy->phy.type == USB_PHY_TYPE_USB3_AND_DP) {

		phy->eq_config5_offset = USB3_DP_PCS_EQ_CONFIG5;

		phy->cdr_reset_time_offset = USB3_DP_PCS_CDR_RESET_TIME;

		phy->phy.reset	= msm_ssphy_qmp_dp_combo_reset;

	}



	if (phy->phy.type == USB_PHY_TYPE_USB3) {

	} else if (phy->phy.type == USB_PHY_TYPE_USB3) {

		phy->eq_config5_offset = USB3_UNI_PCS_EQ_CONFIG5;

		phy->cdr_reset_time_offset = USB3_UNI_PCS_CDR_RESET_TIME;

	}



	phy->link_training_reset = of_property_read_bool(dev->of_node,