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Commit 3e91f3ea authored by Jeremy Linton's avatar Jeremy Linton Committed by Greg Kroah-Hartman
Browse files

arm64: Always enable spectre-v2 vulnerability detection 



[ Upstream commit 8c1e3d2bb44cbb998cb28ff9a18f105fee7f1eb3 ]

Ensure we are always able to detect whether or not the CPU is affected
by Spectre-v2, so that we can later advertise this to userspace.

Signed-off-by: default avatarJeremy Linton <jeremy.linton@arm.com>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 806ac9a7

arch/arm64/kernel/cpu_errata.c

+8 −7
Original line number Diff line number Diff line
@@ -76,7 +76,6 @@ cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused) 
	config_sctlr_el1(SCTLR_EL1_UCT, 0);

}



#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

#include <asm/mmu_context.h>

#include <asm/cacheflush.h>
@@ -217,11 +216,11 @@ static int detect_harden_bp_fw(void) 
	    ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))

		cb = qcom_link_stack_sanitization;



	if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR))

		install_bp_hardening_cb(cb, smccc_start, smccc_end);



	return 1;

}

#endif	/* CONFIG_HARDEN_BRANCH_PREDICTOR */



DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
@@ -457,7 +456,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, 
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\

	CAP_MIDR_RANGE_LIST(midr_list)



#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

/*

 * List of CPUs that do not need any Spectre-v2 mitigation at all.

 */
@@ -489,6 +487,12 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) 
	if (!need_wa)

		return false;



	if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) {

		pr_warn_once("spectrev2 mitigation disabled by kernel configuration\n");

		__hardenbp_enab = false;

		return false;

	}



	/* forced off */

	if (__nospectre_v2) {

		pr_info_once("spectrev2 mitigation disabled by command line option\n");
@@ -500,7 +504,6 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) 


	return (need_wa > 0);

}

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#if	defined(CONFIG_ARM64_ERRATUM_826319) || \
@@ -640,13 +643,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),

	},

#endif

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = check_branch_predictor,

	},

#endif

	{

		.desc = "Speculative Store Bypass Disable",

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,