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Commit 3db9e860 authored by Soren Brinkmann's avatar Soren Brinkmann Committed by Michal Simek
Browse files

arm: zynq: slcr: Use read-modify-write for register writes 



zynq_slcr_cpu_start/stop() ignored the current register state when
writing to a register. Fixing this by implementing proper
read-modify-write.

Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent b5f177ff

arch/arm/mach-zynq/slcr.c

+8 −8
Original line number Diff line number Diff line
@@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void) 
 */

void zynq_slcr_cpu_start(int cpu)

{

	/* enable CPUn */

	writel(SLCR_A9_CPU_CLKSTOP << cpu,

	       zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

	/* enable CLK for CPUn */

	writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

	u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

	reg &= ~(SLCR_A9_CPU_RST << cpu);

	writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

	reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);

	writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

}



/**
@@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu) 
 */

void zynq_slcr_cpu_stop(int cpu)

{

	/* stop CLK and reset CPUn */

	writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,

	       zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

	u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

	reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;

	writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);

}



/**