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Commit 3bcd7fa3 authored by Bruce Allan's avatar Bruce Allan Committed by Jeff Kirsher
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ice: Update to interrupts enabled in OICR 



Remove the following interrupt causes that are not applicable or not
handled:
- PFINT_OICR_HLP_RDY_M
- PFINT_OICR_CPM_RDY_M
- PFINT_OICR_GPIO_M
- PFINT_OICR_STORM_DETECT_M

Add the following interrupt cause that's actually handled in ice_misc_intr:
- PFINT_OICR_PE_CRITERR_M

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: default avatarTony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 5d8778d8

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

+0 −8
Original line number Diff line number Diff line
@@ -121,10 +121,6 @@ 
#define PFINT_FW_CTL_CAUSE_ENA_S	30

#define PFINT_FW_CTL_CAUSE_ENA_M	BIT(PFINT_FW_CTL_CAUSE_ENA_S)

#define PFINT_OICR			0x0016CA00

#define PFINT_OICR_HLP_RDY_S		14

#define PFINT_OICR_HLP_RDY_M		BIT(PFINT_OICR_HLP_RDY_S)

#define PFINT_OICR_CPM_RDY_S		15

#define PFINT_OICR_CPM_RDY_M		BIT(PFINT_OICR_CPM_RDY_S)

#define PFINT_OICR_ECC_ERR_S		16

#define PFINT_OICR_ECC_ERR_M		BIT(PFINT_OICR_ECC_ERR_S)

#define PFINT_OICR_MAL_DETECT_S		19
@@ -133,10 +129,6 @@ 
#define PFINT_OICR_GRST_M		BIT(PFINT_OICR_GRST_S)

#define PFINT_OICR_PCI_EXCEPTION_S	21

#define PFINT_OICR_PCI_EXCEPTION_M	BIT(PFINT_OICR_PCI_EXCEPTION_S)

#define PFINT_OICR_GPIO_S		22

#define PFINT_OICR_GPIO_M		BIT(PFINT_OICR_GPIO_S)

#define PFINT_OICR_STORM_DETECT_S	24

#define PFINT_OICR_STORM_DETECT_M	BIT(PFINT_OICR_STORM_DETECT_S)

#define PFINT_OICR_HMC_ERR_S		26

#define PFINT_OICR_HMC_ERR_M		BIT(PFINT_OICR_HMC_ERR_S)

#define PFINT_OICR_PE_CRITERR_S		28

drivers/net/ethernet/intel/ice/ice_main.c

+3 −6
Original line number Diff line number Diff line
@@ -1704,15 +1704,12 @@ static void ice_ena_misc_vector(struct ice_pf *pf) 
	wr32(hw, PFINT_OICR_ENA, 0);	/* disable all */

	rd32(hw, PFINT_OICR);		/* read to clear */



	val = (PFINT_OICR_HLP_RDY_M |

	       PFINT_OICR_CPM_RDY_M |

	       PFINT_OICR_ECC_ERR_M |

	val = (PFINT_OICR_ECC_ERR_M |

	       PFINT_OICR_MAL_DETECT_M |

	       PFINT_OICR_GRST_M |

	       PFINT_OICR_PCI_EXCEPTION_M |

	       PFINT_OICR_GPIO_M |

	       PFINT_OICR_STORM_DETECT_M |

	       PFINT_OICR_HMC_ERR_M);

	       PFINT_OICR_HMC_ERR_M |

	       PFINT_OICR_PE_CRITERR_M);



	wr32(hw, PFINT_OICR_ENA, val);