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Commit 3b6d9fd2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices 



Only DCE5+ asics support DP 1.2.

Noticed by ArtForz on IRC.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent af5d3653

drivers/gpu/drm/radeon/atombios_dp.c

+15 −2
Original line number Diff line number Diff line
@@ -291,6 +291,19 @@ static int dp_get_max_dp_pix_clock(int link_rate, 


/***** radeon specific DP functions *****/



static int radeon_dp_get_max_link_rate(struct drm_connector *connector,

				       u8 dpcd[DP_DPCD_SIZE])

{

	int max_link_rate;



	if (radeon_connector_is_dp12_capable(connector))

		max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);

	else

		max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);



	return max_link_rate;

}



/* First get the min lane# when low rate is used according to pixel clock

 * (prefer low rate), second check max lane# supported by DP panel,

 * if the max lane# < low rate lane# then use max lane# instead.
@@ -300,7 +313,7 @@ static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 
					int pix_clock)

{

	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));

	int max_link_rate = drm_dp_max_link_rate(dpcd);

	int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);

	int max_lane_num = drm_dp_max_lane_count(dpcd);

	int lane_num;

	int max_dp_pix_clock;
@@ -338,7 +351,7 @@ static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, 
			return 540000;

	}



	return drm_dp_max_link_rate(dpcd);

	return radeon_dp_get_max_link_rate(connector, dpcd);

}



static u8 radeon_dp_encoder_service(struct radeon_device *rdev,