Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3b31b8f1 authored by Saikumar's avatar Saikumar
Browse files

Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14 



* quic/dev/msm-4.14-display:
  drm: msm: dp: correct the resolution width check in get_mode_info
  drm: msm: dp: Update correct count for mst encoder count
  drm/msm/sde : initialize rsc_state and wait_refcount

Change-Id: I86ce4140700067484952bcd1bd4425c77e4f4dc0
Signed-off-by: default avatarSaikumar <saikk@codeaurora.org>
parent e9808ac2

drivers/gpu/drm/msm/dp/dp_display.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -1297,6 +1297,7 @@ static int dp_init_sub_modules(struct dp_display_private *dp) 
	}

	}





	g_dp_display->is_mst_supported = dp->parser->has_mst;

	g_dp_display->is_mst_supported = dp->parser->has_mst;

	g_dp_display->no_mst_encoder = dp->parser->no_mst_encoder;





	dp->catalog = dp_catalog_get(dev, dp->parser);

	dp->catalog = dp_catalog_get(dev, dp->parser);

	if (IS_ERR(dp->catalog)) {

	if (IS_ERR(dp->catalog)) {
@@ -2700,6 +2701,9 @@ int dp_display_get_num_of_displays(void) 




int dp_display_get_num_of_streams(void)

int dp_display_get_num_of_streams(void)

{

{

	if (g_dp_display->no_mst_encoder)

		return 0;



	return DP_STREAM_MAX;

	return DP_STREAM_MAX;

}

}

drivers/gpu/drm/msm/dp/dp_display.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -78,6 +78,7 @@ struct dp_display { 
	u32 max_pclk_khz;

	u32 max_pclk_khz;

	u32 max_hdisplay;

	u32 max_hdisplay;

	u32 max_vdisplay;

	u32 max_vdisplay;

	u32 no_mst_encoder;

	void *dp_mst_prv_info;

	void *dp_mst_prv_info;





	int (*enable)(struct dp_display *dp_display, void *panel);

	int (*enable)(struct dp_display *dp_display, void *panel);

drivers/gpu/drm/msm/dp/dp_parser.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -726,6 +726,8 @@ static int dp_parser_mst(struct dp_parser *parser) 




	parser->has_mst = of_property_read_bool(dev->of_node,

	parser->has_mst = of_property_read_bool(dev->of_node,

			"qcom,mst-enable");

			"qcom,mst-enable");

	parser->no_mst_encoder = of_property_read_bool(dev->of_node,

			"qcom,no-mst-encoder");

	parser->has_mst_sideband = parser->has_mst;

	parser->has_mst_sideband = parser->has_mst;





	pr_debug("mst parsing successful. mst:%d\n", parser->has_mst);

	pr_debug("mst parsing successful. mst:%d\n", parser->has_mst);

drivers/gpu/drm/msm/dp/dp_parser.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -197,6 +197,7 @@ static inline char *dp_phy_aux_config_type_to_string(u32 cfg_type) 
 * @max_lclk_khz: maximum link clock supported for the platform

 * @max_lclk_khz: maximum link clock supported for the platform

 * @max_hdisplay: maximum supported horizontal display by the platform for dp

 * @max_hdisplay: maximum supported horizontal display by the platform for dp

 * @max_vdisplay: maximum supported vertical display by the platform for dp

 * @max_vdisplay: maximum supported vertical display by the platform for dp

 * @no_mst_encoder: zero mst encoders should be initialised for platform

 * @hw_cfg: DP HW specific settings

 * @hw_cfg: DP HW specific settings

 * @has_mst: MST feature enable status

 * @has_mst: MST feature enable status

 * @has_mst_sideband: MST sideband feature enable status

 * @has_mst_sideband: MST sideband feature enable status
@@ -228,6 +229,7 @@ struct dp_parser { 
	u32 max_lclk_khz;

	u32 max_lclk_khz;

	u32 max_hdisplay;

	u32 max_hdisplay;

	u32 max_vdisplay;

	u32 max_vdisplay;

	bool no_mst_encoder;

	struct dp_hw_cfg hw_cfg;

	struct dp_hw_cfg hw_cfg;

	bool has_mst;

	bool has_mst;

	bool has_mst_sideband;

	bool has_mst_sideband;

drivers/gpu/drm/msm/sde/sde_encoder.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -1900,7 +1900,7 @@ static int _sde_encoder_update_rsc_client( 
{

{

	struct sde_encoder_virt *sde_enc;

	struct sde_encoder_virt *sde_enc;

	struct drm_crtc *crtc;

	struct drm_crtc *crtc;

	enum sde_rsc_state rsc_state;

	enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;

	struct sde_rsc_cmd_config *rsc_config;

	struct sde_rsc_cmd_config *rsc_config;

	int ret, prefill_lines;

	int ret, prefill_lines;

	struct msm_display_info *disp_info;

	struct msm_display_info *disp_info;
@@ -1910,7 +1910,7 @@ static int _sde_encoder_update_rsc_client( 
	struct drm_crtc *primary_crtc;

	struct drm_crtc *primary_crtc;

	int pipe = -1;

	int pipe = -1;

	int rc = 0;

	int rc = 0;

	int wait_refcount;

	int wait_refcount = 0;

	u32 qsync_mode = 0;

	u32 qsync_mode = 0;





	if (!drm_enc || !drm_enc->dev) {

	if (!drm_enc || !drm_enc->dev) {