Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 38b3a2b2 authored by Guru Das Srinagesh's avatar Guru Das Srinagesh
Browse files

power: qpnp-fg-gen4: Add DT support for Ki current thresh coefficients 



Add support for device tree properties to configure low-to-medium and
medium-to-high current thresholds for charging and discharging states.
Also group related SRAM writes into a separate function to reduce
cyclomatic complexity of fg_gen4_hw_init().

Change-Id: If837855f588e5ef5e2268de9e74468cf42a45a55
Signed-off-by: default avatarGuru Das Srinagesh <gurus@codeaurora.org>
parent c2a9e9f5

drivers/power/supply/qcom/fg-core.h

+4 −0
Original line number Diff line number Diff line
@@ -209,9 +209,13 @@ enum fg_sram_param_id { 
	FG_SRAM_KI_COEFF_LOW_DISCHG,

	FG_SRAM_KI_COEFF_MED_DISCHG,

	FG_SRAM_KI_COEFF_HI_DISCHG,

	FG_SRAM_KI_COEFF_LO_MED_DCHG_THR,

	FG_SRAM_KI_COEFF_MED_HI_DCHG_THR,

	FG_SRAM_KI_COEFF_LOW_CHG,

	FG_SRAM_KI_COEFF_MED_CHG,

	FG_SRAM_KI_COEFF_HI_CHG,

	FG_SRAM_KI_COEFF_LO_MED_CHG_THR,

	FG_SRAM_KI_COEFF_MED_HI_CHG_THR,

	FG_SRAM_KI_COEFF_FULL_SOC,

	FG_SRAM_KI_COEFF_CUTOFF,

	FG_SRAM_ESR_TIGHT_FILTER,

drivers/power/supply/qcom/qpnp-fg-gen4.c

+171 −58
Original line number Diff line number Diff line
@@ -99,12 +99,20 @@ 
#define KI_COEFF_MED_DISCHG_OFFSET	0

#define KI_COEFF_HI_DISCHG_WORD		26

#define KI_COEFF_HI_DISCHG_OFFSET	1

#define KI_COEFF_LO_MED_DCHG_THR_WORD	27

#define KI_COEFF_LO_MED_DCHG_THR_OFFSET	0

#define KI_COEFF_MED_HI_DCHG_THR_WORD	27

#define KI_COEFF_MED_HI_DCHG_THR_OFFSET	1

#define KI_COEFF_LOW_CHG_WORD		28

#define KI_COEFF_LOW_CHG_OFFSET		0

#define KI_COEFF_MED_CHG_WORD		28

#define KI_COEFF_MED_CHG_OFFSET		1

#define KI_COEFF_HI_CHG_WORD		29

#define KI_COEFF_HI_CHG_OFFSET		0

#define KI_COEFF_LO_MED_CHG_THR_WORD	29

#define KI_COEFF_LO_MED_CHG_THR_OFFSET	1

#define KI_COEFF_MED_HI_CHG_THR_WORD	30

#define KI_COEFF_MED_HI_CHG_THR_OFFSET	0

#define DELTA_BSOC_THR_WORD		30

#define DELTA_BSOC_THR_OFFSET		1

#define SLOPE_LIMIT_WORD		32
@@ -241,12 +249,16 @@ struct fg_dt_props { 
	int	ki_coeff_low_chg;

	int	ki_coeff_med_chg;

	int	ki_coeff_hi_chg;

	int	ki_coeff_lo_med_chg_thr_ma;

	int	ki_coeff_med_hi_chg_thr_ma;

	int	ki_coeff_cutoff_gain;

	int	ki_coeff_full_soc_dischg[2];

	int	ki_coeff_soc[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_low_dischg[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_med_dischg[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_hi_dischg[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_lo_med_dchg_thr_ma;

	int	ki_coeff_med_hi_dchg_thr_ma;

	int	slope_limit_coeffs[SLOPE_LIMIT_NUM_COEFFS];

};
@@ -506,12 +518,24 @@ static struct fg_sram_param pm8150b_v2_sram_params[] = { 
	PARAM(KI_COEFF_HI_DISCHG, KI_COEFF_HI_DISCHG_WORD,

		KI_COEFF_HI_DISCHG_OFFSET, 1, 1000, 61035, 0,

		fg_encode_default, NULL),

	PARAM(KI_COEFF_LO_MED_DCHG_THR, KI_COEFF_LO_MED_DCHG_THR_WORD,

		KI_COEFF_LO_MED_DCHG_THR_OFFSET, 1, 1000, 15625, 0,

		fg_encode_default, NULL),

	PARAM(KI_COEFF_MED_HI_DCHG_THR, KI_COEFF_MED_HI_DCHG_THR_WORD,

		KI_COEFF_MED_HI_DCHG_THR_OFFSET, 1, 1000, 15625, 0,

		fg_encode_default, NULL),

	PARAM(KI_COEFF_LOW_CHG, KI_COEFF_LOW_CHG_WORD, KI_COEFF_LOW_CHG_OFFSET,

		1, 1000, 61035, 0, fg_encode_default, NULL),

	PARAM(KI_COEFF_MED_CHG, KI_COEFF_MED_CHG_WORD, KI_COEFF_MED_CHG_OFFSET,

		1, 1000, 61035, 0, fg_encode_default, NULL),

	PARAM(KI_COEFF_HI_CHG, KI_COEFF_HI_CHG_WORD, KI_COEFF_HI_CHG_OFFSET, 1,

		1000, 61035, 0, fg_encode_default, NULL),

	PARAM(KI_COEFF_LO_MED_CHG_THR, KI_COEFF_LO_MED_CHG_THR_WORD,

		KI_COEFF_LO_MED_CHG_THR_OFFSET, 1, 1000, 15625, 0,

		fg_encode_default, NULL),

	PARAM(KI_COEFF_MED_HI_CHG_THR, KI_COEFF_MED_HI_CHG_THR_WORD,

		KI_COEFF_MED_HI_CHG_THR_OFFSET, 1, 1000, 15625, 0,

		fg_encode_default, NULL),

	PARAM(SLOPE_LIMIT, SLOPE_LIMIT_WORD, SLOPE_LIMIT_OFFSET, 1, 8192,

		1000000, 0, fg_encode_default, NULL),

	PARAM(BATT_TEMP_COLD, BATT_TEMP_CONFIG_WORD, BATT_TEMP_COLD_OFFSET, 1,
@@ -4806,6 +4830,134 @@ static int fg_gen4_esr_calib_config(struct fg_gen4_chip *chip) 
	return rc;

}



static int fg_gen4_init_ki_coeffts(struct fg_gen4_chip *chip)

{

	int rc;

	u8 val;

	struct fg_dev *fg = &chip->fg;



	if (chip->dt.ki_coeff_low_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_LOW_CHG,

			chip->dt.ki_coeff_low_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_low_chg, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_med_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_CHG,

			chip->dt.ki_coeff_med_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_med_chg, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_hi_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_HI_CHG,

			chip->dt.ki_coeff_hi_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_hi_chg, rc=%d\n", rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_lo_med_chg_thr_ma != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_LO_MED_CHG_THR,

			chip->dt.ki_coeff_lo_med_chg_thr_ma, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_LO_MED_CHG_THR].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_LO_MED_CHG_THR].addr_byte,

			&val, fg->sp[FG_SRAM_KI_COEFF_LO_MED_CHG_THR].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_lo_med_chg_thr_ma, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_med_hi_chg_thr_ma != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_HI_CHG_THR,

			chip->dt.ki_coeff_med_hi_chg_thr_ma, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_CHG_THR].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_CHG_THR].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_CHG_THR].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_med_hi_chg_thr_ma, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_lo_med_dchg_thr_ma != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_LO_MED_DCHG_THR,

			chip->dt.ki_coeff_lo_med_dchg_thr_ma, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_LO_MED_DCHG_THR].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_LO_MED_DCHG_THR].addr_byte,

			&val, fg->sp[FG_SRAM_KI_COEFF_LO_MED_DCHG_THR].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_lo_med_dchg_thr_ma, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_med_hi_dchg_thr_ma != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_HI_DCHG_THR,

			chip->dt.ki_coeff_med_hi_dchg_thr_ma, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_DCHG_THR].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_DCHG_THR].addr_byte,

			&val, fg->sp[FG_SRAM_KI_COEFF_MED_HI_DCHG_THR].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_med_hi_dchg_thr_ma, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_cutoff_gain != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_CUTOFF,

			  chip->dt.ki_coeff_cutoff_gain, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_cutoff_gain, rc=%d\n",

				rc);

			return rc;

		}

	}



	return 0;

}



#define BATT_TEMP_HYST_MASK	GENMASK(3, 0)

#define BATT_TEMP_DELTA_MASK	GENMASK(7, 4)

#define BATT_TEMP_DELTA_SHIFT	4
@@ -5006,64 +5158,9 @@ static int fg_gen4_hw_init(struct fg_gen4_chip *chip) 
		}

	}



	if (chip->dt.ki_coeff_low_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_LOW_CHG,

			chip->dt.ki_coeff_low_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_low_chg, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_med_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_CHG,

			chip->dt.ki_coeff_med_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_med_chg, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_hi_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_HI_CHG,

			chip->dt.ki_coeff_hi_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_hi_chg, rc=%d\n", rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_cutoff_gain != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_CUTOFF,

			  chip->dt.ki_coeff_cutoff_gain, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_cutoff_gain, rc=%d\n",

				rc);

	rc = fg_gen4_init_ki_coeffts(chip);

	if (rc < 0)

		return rc;

		}

	}



	rc = fg_gen4_esr_calib_config(chip);

	if (rc < 0)
@@ -5153,6 +5250,22 @@ static int fg_parse_ki_coefficients(struct fg_dev *fg) 
	of_property_read_u32(node, "qcom,ki-coeff-hi-chg",

		&chip->dt.ki_coeff_hi_chg);



	chip->dt.ki_coeff_lo_med_chg_thr_ma = 1000;

	of_property_read_u32(node, "qcom,ki-coeff-chg-low-med-thresh-ma",

		&chip->dt.ki_coeff_lo_med_chg_thr_ma);



	chip->dt.ki_coeff_med_hi_chg_thr_ma = 1500;

	of_property_read_u32(node, "qcom,ki-coeff-chg-med-hi-thresh-ma",

		&chip->dt.ki_coeff_med_hi_chg_thr_ma);



	chip->dt.ki_coeff_lo_med_dchg_thr_ma = 50;

	of_property_read_u32(node, "qcom,ki-coeff-dischg-low-med-thresh-ma",

		&chip->dt.ki_coeff_lo_med_dchg_thr_ma);



	chip->dt.ki_coeff_med_hi_dchg_thr_ma = 100;

	of_property_read_u32(node, "qcom,ki-coeff-dischg-med-hi-thresh-ma",

		&chip->dt.ki_coeff_med_hi_dchg_thr_ma);



	chip->dt.ki_coeff_cutoff_gain = -EINVAL;

	of_property_read_u32(node, "qcom,ki-coeff-cutoff",

		&chip->dt.ki_coeff_cutoff_gain);