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Commit 362ed48d authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux 

Pull clock framework update from Michael Turquette:
 "The common clock framework changes for 3.10 include many fixes for
  existing platforms, as well as adoption of the framework by new
  platforms and devices.

  Some long-needed fixes to the core framework are here as well as new
  features such as improved initialization of clocks from DT as well as
  framework reentrancy for nested clock operations."

* tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux: (44 commits)
  clk: add clk_ignore_unused option to keep boot clocks on
  clk: ux500: fix mismatched types
  clk: vexpress: Add separate SP810 driver
  clk: si5351: make clk-si5351 depend on CONFIG_OF
  clk: export __clk_get_flags for modular clock providers
  clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate.
  clk: sunxi: Unify oscillator clock
  clk: composite: allow fixed rates & fixed dividers
  clk: composite: rename 'div' references to 'rate'
  clk: add si5351 i2c common clock driver
  clk: add device tree fixed-factor-clock binding support
  clk: Properly handle notifier return values
  clk: ux500: abx500: Define clock tree for ab850x
  clk: ux500: Add support for sysctrl clocks
  clk: mvebu: Fix valid value range checking for cpu_freq_select
  clk: Fixup locking issues for clk_set_parent
  clk: Fixup errorhandling for clk_set_parent
  clk: Restructure code for __clk_reparent
  clk: sunxi: drop an unnecesary kmalloc
  clk: sunxi: drop CLK_IGNORE_UNUSED
  ...
parents 61f3d0a9 1e435256

Documentation/arm/sunxi/clocks.txt

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Frequently asked questions about the sunxi clock system

=======================================================



This document contains useful bits of information that people tend to ask

about the sunxi clock system, as well as accompanying ASCII art when adequate.



Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the

   system?



A: The 24MHz oscillator allows gating to save power. Indeed, if gated

   carelessly the system would stop functioning, but with the right

   steps, one can gate it and keep the system running. Consider this

   simplified suspend example:



   While the system is operational, you would see something like



      24MHz         32kHz

       |

      PLL1

       \

        \_ CPU Mux

             |

           [CPU]



   When you are about to suspend, you switch the CPU Mux to the 32kHz

   oscillator:



      24Mhz         32kHz

       |              |

      PLL1            |

                     /

           CPU Mux _/

             |

           [CPU]



    Finally you can gate the main oscillator



                    32kHz

                      |

                      |

                     /

           CPU Mux _/

             |

           [CPU]



Q: Were can I learn more about the sunxi clocks?



A: The linux-sunxi wiki contains a page documenting the clock registers,

   you can find it at



        http://linux-sunxi.org/A10/CCM



   The authoritative source for information at this time is the ccmu driver

   released by Allwinner, you can find it at



        https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu

Documentation/clk.txt

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@@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw) 
};

};





Below is a matrix detailing which clk_ops are mandatory based upon the

Below is a matrix detailing which clk_ops are mandatory based upon the

hardware capbilities of that clock.  A cell marked as "y" means

hardware capabilities of that clock.  A cell marked as "y" means

mandatory, a cell marked as "n" implies that either including that

mandatory, a cell marked as "n" implies that either including that

callback is invalid or otherwise uneccesary.  Empty cells are either

callback is invalid or otherwise unnecessary.  Empty cells are either

optional or must be evaluated on a case-by-case basis.

optional or must be evaluated on a case-by-case basis.





                           clock hardware characteristics

                           clock hardware characteristics
@@ -231,3 +231,14 @@ To better enforce this policy, always follow this simple rule: any 
statically initialized clock data MUST be defined in a separate file

statically initialized clock data MUST be defined in a separate file

from the logic that implements its ops.  Basically separate the logic

from the logic that implements its ops.  Basically separate the logic

from the data and all is well.

from the data and all is well.



	Part 6 - Disabling clock gating of unused clocks



Sometimes during development it can be useful to be able to bypass the

default disabling of unused clocks. For example, if drivers aren't enabling

clocks properly but rely on them being on from the bootloader, bypassing

the disabling means that the driver will remain functional while the issues

are sorted out.



To bypass this disabling, include "clk_ignore_unused" in the bootargs to the

kernel.

Documentation/devicetree/bindings/clock/axi-clkgen.txt

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Binding for the axi-clkgen clock generator



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "adi,axi-clkgen".

- #clock-cells : from common clock binding; Should always be set to 0.

- reg : Address and length of the axi-clkgen register set.

- clocks : Phandle and clock specifier for the parent clock.



Optional properties:

- clock-output-names : From common clock binding.



Example:

	clock@0xff000000 {

		compatible = "adi,axi-clkgen";

		#clock-cells = <0>;

		reg = <0xff000000 0x1000>;

		clocks = <&osc 1>;

	};

Documentation/devicetree/bindings/clock/fixed-factor-clock.txt

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Binding for simple fixed factor rate clock sources.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "fixed-factor-clock".

- #clock-cells : from common clock binding; shall be set to 0.

- clock-div: fixed divider.

- clock-mult: fixed multiplier.

- clocks: parent clock.



Optional properties:

- clock-output-names : From common clock binding.



Example:

	clock {

		compatible = "fixed-factor-clock";

		clocks = <&parentclk>;

		#clock-cells = <0>;

		div = <2>;

		mult = <1>;

	};

Documentation/devicetree/bindings/clock/silabs,si5351.txt

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Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.



Reference

[1] Si5351A/B/C Data Sheet

    http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf



The Si5351a/b/c are programmable i2c clock generators with upto 8 output

clocks. Si5351a also has a reduced pin-count package (MSOP10) where only

3 output clocks are accessible. The internal structure of the clock

generators can be found in [1].



==I2C device node==



Required properties:

- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".

- reg: i2c device address, shall be 0x60 or 0x61.

- #clock-cells: from common clock binding; shall be set to 1.

- clocks: from common clock binding; list of parent clock

  handles, shall be xtal reference clock or xtal and clkin for

  si5351c only.

- #address-cells: shall be set to 1.

- #size-cells: shall be set to 0.



Optional properties:

- silabs,pll-source: pair of (number, source) for each pll. Allows

  to overwrite clock source of pll A (number=0) or B (number=1).



==Child nodes==



Each of the clock outputs can be overwritten individually by

using a child node to the I2C device node. If a child node for a clock

output is not set, the eeprom configuration is not overwritten.



Required child node properties:

- reg: number of clock output.



Optional child node properties:

- silabs,clock-source: source clock of the output divider stage N, shall be

  0 = multisynth N

  1 = multisynth 0 for output clocks 0-3, else multisynth4

  2 = xtal

  3 = clkin (si5351c only)

- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.

- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth

  divider.

- silabs,pll-master: boolean, multisynth can change pll frequency.



==Example==



/* 25MHz reference crystal */

ref25: ref25M {

	compatible = "fixed-clock";

	#clock-cells = <0>;

	clock-frequency = <25000000>;

};



i2c-master-node {



	/* Si5351a msop10 i2c clock generator */

	si5351a: clock-generator@60 {

		compatible = "silabs,si5351a-msop";

		reg = <0x60>;

		#address-cells = <1>;

		#size-cells = <0>;

		#clock-cells = <1>;



		/* connect xtal input to 25MHz reference */

		clocks = <&ref25>;



		/* connect xtal input as source of pll0 and pll1 */

		silabs,pll-source = <0 0>, <1 0>;



		/*

		 * overwrite clkout0 configuration with:

		 * - 8mA output drive strength

		 * - pll0 as clock source of multisynth0

		 * - multisynth0 as clock source of output divider

		 * - multisynth0 can change pll0

		 * - set initial clock frequency of 74.25MHz

		 */

		clkout0 {

			reg = <0>;

			silabs,drive-strength = <8>;

			silabs,multisynth-source = <0>;

			silabs,clock-source = <0>;

			silabs,pll-master;

			clock-frequency = <74250000>;

		};



		/*

		 * overwrite clkout1 configuration with:

		 * - 4mA output drive strength

		 * - pll1 as clock source of multisynth1

		 * - multisynth1 as clock source of output divider

		 * - multisynth1 can change pll1

		 */

		clkout1 {

			reg = <1>;

			silabs,drive-strength = <4>;

			silabs,multisynth-source = <1>;

			silabs,clock-source = <0>;

			pll-master;

		};



		/*

		 * overwrite clkout2 configuration with:

		 * - xtal as clock source of output divider

		 */

		clkout2 {

			reg = <2>;

			silabs,clock-source = <2>;

		};

	};

};