Loading arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi +3 −2 Original line number Diff line number Diff line Loading @@ -343,9 +343,10 @@ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; clock-names = "aux_clk", "pipe_clk", "ref_clk_src", "ref_clk", "com_aux_clk"; "ref_clk", "com_aux_clk", "cfg_ahb_clk"; resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; Loading Loading
arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi +3 −2 Original line number Diff line number Diff line Loading @@ -343,9 +343,10 @@ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; clock-names = "aux_clk", "pipe_clk", "ref_clk_src", "ref_clk", "com_aux_clk"; "ref_clk", "com_aux_clk", "cfg_ahb_clk"; resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; Loading