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Commit 345a3f69 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: gcc-sdm855: Remove the QUP core clock support 



The QUP core clocks do not need to be voted on from Linux.
The branch clocks will be controlled by RPMh and executing
entities can scale them via their BCM votes.

Change-Id: I5b2976ae52705e0e527393f13369162a64aa45ef
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent b2bdf7dc

drivers/clk/qcom/gcc-sdm855.c

+23 −168
Original line number Diff line number Diff line
@@ -122,31 +122,15 @@ static const char * const gcc_parent_names_3[] = { 


static const struct parent_map gcc_parent_map_4[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL1_OUT_MAIN, 4 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_4[] = {

	"bi_tcxo",

	"gpll0",

	"gpll1",

	"gpll0_out_even",

	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_5[] = {

	{ P_BI_TCXO, 0 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_5[] = {

	"bi_tcxo",

	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_6[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL2_OUT_MAIN, 2 },
@@ -157,7 +141,7 @@ static const struct parent_map gcc_parent_map_6[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_6[] = {

static const char * const gcc_parent_names_5[] = {

	"bi_tcxo",

	"gpll0",

	"gpll2",
@@ -168,7 +152,7 @@ static const char * const gcc_parent_names_6[] = { 
	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_7[] = {

static const struct parent_map gcc_parent_map_6[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL7_OUT_MAIN, 3 },
@@ -176,7 +160,7 @@ static const struct parent_map gcc_parent_map_7[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_7[] = {

static const char * const gcc_parent_names_6[] = {

	"bi_tcxo",

	"gpll0",

	"gpll7",
@@ -184,7 +168,7 @@ static const char * const gcc_parent_names_7[] = { 
	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_8[] = {

static const struct parent_map gcc_parent_map_7[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL9_OUT_MAIN, 2 },
@@ -193,7 +177,7 @@ static const struct parent_map gcc_parent_map_8[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_8[] = {

static const char * const gcc_parent_names_7[] = {

	"bi_tcxo",

	"gpll0",

	"gpll9",
@@ -202,7 +186,7 @@ static const char * const gcc_parent_names_8[] = { 
	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_9[] = {

static const struct parent_map gcc_parent_map_8[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_AUD_REF_CLK, 2 },
@@ -210,7 +194,7 @@ static const struct parent_map gcc_parent_map_9[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_9[] = {

static const char * const gcc_parent_names_8[] = {

	"bi_tcxo",

	"gpll0",

	"aud_ref_clk",
@@ -446,11 +430,11 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = { 
	.cmd_rcgr = 0x6038,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_7,

	.parent_map = gcc_parent_map_6,

	.freq_tbl = ftbl_gcc_emac_ptp_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_emac_ptp_clk_src",

		.parent_names = gcc_parent_names_7,

		.parent_names = gcc_parent_names_6,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -468,11 +452,11 @@ static struct clk_rcg2 gcc_emac_rgmii_clk_src = { 
	.cmd_rcgr = 0x601c,

	.mnd_width = 8,

	.hid_width = 5,

	.parent_map = gcc_parent_map_7,

	.parent_map = gcc_parent_map_6,

	.freq_tbl = ftbl_gcc_emac_ptp_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_emac_rgmii_clk_src",

		.parent_names = gcc_parent_names_7,

		.parent_names = gcc_parent_names_6,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -576,11 +560,11 @@ static struct clk_rcg2 gcc_npu_axi_clk_src = { 
	.cmd_rcgr = 0x4d014,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_6,

	.parent_map = gcc_parent_map_5,

	.freq_tbl = ftbl_gcc_npu_axi_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_npu_axi_clk_src",

		.parent_names = gcc_parent_names_6,

		.parent_names = gcc_parent_names_5,

		.num_parents = 8,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -921,38 +905,6 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 
	},

};



static const struct freq_tbl ftbl_gcc_qupv3_wrap1_core_2x_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),

	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),

	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),

	{ }

};



static struct clk_rcg2 gcc_qupv3_wrap1_core_2x_clk_src = {

	.cmd_rcgr = 0x18018,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_4,

	.freq_tbl = ftbl_gcc_qupv3_wrap1_core_2x_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qupv3_wrap1_core_2x_clk_src",

		.parent_names = gcc_parent_names_4,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200000,

			[VDD_LOWER] = 50000000,

			[VDD_LOW] = 100000000,

			[VDD_LOW_L1] = 150000000,

			[VDD_NOMINAL] = 200000000},

	},

};



static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {

	.cmd_rcgr = 0x18148,

	.mnd_width = 16,
@@ -1232,11 +1184,11 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 
	.cmd_rcgr = 0x1400c,

	.mnd_width = 8,

	.hid_width = 5,

	.parent_map = gcc_parent_map_8,

	.parent_map = gcc_parent_map_7,

	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_sdcc2_apps_clk_src",

		.parent_names = gcc_parent_names_8,

		.parent_names = gcc_parent_names_7,

		.num_parents = 6,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -1263,11 +1215,11 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 
	.cmd_rcgr = 0x1600c,

	.mnd_width = 8,

	.hid_width = 5,

	.parent_map = gcc_parent_map_4,

	.parent_map = gcc_parent_map_3,

	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_sdcc4_apps_clk_src",

		.parent_names = gcc_parent_names_4,

		.parent_names = gcc_parent_names_3,

		.num_parents = 3,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -1289,11 +1241,11 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = { 
	.cmd_rcgr = 0x36010,

	.mnd_width = 8,

	.hid_width = 5,

	.parent_map = gcc_parent_map_9,

	.parent_map = gcc_parent_map_8,

	.freq_tbl = ftbl_gcc_tsif_ref_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_tsif_ref_clk_src",

		.parent_names = gcc_parent_names_9,

		.parent_names = gcc_parent_names_8,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -1376,12 +1328,12 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 
	.cmd_rcgr = 0x75094,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_5,

	.parent_map = gcc_parent_map_4,

	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,

	.flags = FORCE_ENABLE_RCG,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_card_phy_aux_clk_src",

		.parent_names = gcc_parent_names_5,

		.parent_names = gcc_parent_names_4,

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -1480,12 +1432,12 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 
	.cmd_rcgr = 0x77094,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_5,

	.parent_map = gcc_parent_map_4,

	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,

	.flags = FORCE_ENABLE_RCG,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_phy_phy_aux_clk_src",

		.parent_names = gcc_parent_names_5,

		.parent_names = gcc_parent_names_4,

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -2740,32 +2692,6 @@ static struct clk_branch gcc_qspi_core_clk = { 
	},

};



static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {

	.halt_reg = 0x17014,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(9),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap0_core_2x_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap0_core_clk = {

	.halt_reg = 0x1700c,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(8),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap0_core_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap0_s0_clk = {

	.halt_reg = 0x17144,

	.halt_check = BRANCH_HALT_VOTED,
@@ -2910,42 +2836,6 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 
	},

};



static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {

	.halt_reg = 0x18014,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(18),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap1_core_2x_clk",

			.parent_names = (const char *[]){

				"gcc_qupv3_wrap1_core_2x_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap1_core_clk = {

	.halt_reg = 0x1800c,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(19),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap1_core_clk",

			.parent_names = (const char *[]){

				"gcc_qupv3_wrap1_core_2x_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap1_s0_clk = {

	.halt_reg = 0x18144,

	.halt_check = BRANCH_HALT_VOTED,
@@ -3054,32 +2944,6 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 
	},

};



static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {

	.halt_reg = 0x1e014,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x52014,

		.enable_mask = BIT(3),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap2_core_2x_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap2_core_clk = {

	.halt_reg = 0x1e00c,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x52014,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap2_core_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap2_s0_clk = {

	.halt_reg = 0x1e144,

	.halt_check = BRANCH_HALT_VOTED,
@@ -4226,8 +4090,6 @@ static struct clk_regmap *gcc_sdm855_clocks[] = { 
	[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,

	[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,

	[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,

	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,

	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,

	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,

	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,

	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
@@ -4244,10 +4106,6 @@ static struct clk_regmap *gcc_sdm855_clocks[] = { 
	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,

	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,

	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,

	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,

	[GCC_QUPV3_WRAP1_CORE_2X_CLK_SRC] =

		&gcc_qupv3_wrap1_core_2x_clk_src.clkr,

	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,

	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,

	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,

	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
@@ -4260,8 +4118,6 @@ static struct clk_regmap *gcc_sdm855_clocks[] = { 
	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,

	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,

	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,

	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,

	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,

	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,

	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,

	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
@@ -4409,7 +4265,6 @@ static struct clk_dfs gcc_dfs_clocks[] = { 
	{ &gcc_qupv3_wrap0_s5_clk_src, DFS_ENABLE_RCG },

	{ &gcc_qupv3_wrap0_s6_clk_src, DFS_ENABLE_RCG },

	{ &gcc_qupv3_wrap0_s7_clk_src, DFS_ENABLE_RCG },

	{ &gcc_qupv3_wrap1_core_2x_clk_src, DFS_ENABLE_RCG },

	{ &gcc_qupv3_wrap1_s0_clk_src, DFS_ENABLE_RCG },

	{ &gcc_qupv3_wrap1_s1_clk_src, DFS_ENABLE_RCG },

	{ &gcc_qupv3_wrap1_s2_clk_src, DFS_ENABLE_RCG },

include/dt-bindings/clock/qcom,gcc-sdm855.h

+122 −129
Original line number Diff line number Diff line
@@ -97,135 +97,128 @@ 
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK				79

#define GCC_QSPI_CORE_CLK					80

#define GCC_QSPI_CORE_CLK_SRC					81

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				82

#define GCC_QUPV3_WRAP0_CORE_CLK				83

#define GCC_QUPV3_WRAP0_S0_CLK					84

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				85

#define GCC_QUPV3_WRAP0_S1_CLK					86

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				87

#define GCC_QUPV3_WRAP0_S2_CLK					88

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				89

#define GCC_QUPV3_WRAP0_S3_CLK					90

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				91

#define GCC_QUPV3_WRAP0_S4_CLK					92

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				93

#define GCC_QUPV3_WRAP0_S5_CLK					94

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				95

#define GCC_QUPV3_WRAP0_S6_CLK					96

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				97

#define GCC_QUPV3_WRAP0_S7_CLK					98

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				99

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				100

#define GCC_QUPV3_WRAP1_CORE_2X_CLK_SRC				101

#define GCC_QUPV3_WRAP1_CORE_CLK				102

#define GCC_QUPV3_WRAP1_S0_CLK					103

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				104

#define GCC_QUPV3_WRAP1_S1_CLK					105

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				106

#define GCC_QUPV3_WRAP1_S2_CLK					107

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				108

#define GCC_QUPV3_WRAP1_S3_CLK					109

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				110

#define GCC_QUPV3_WRAP1_S4_CLK					111

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				112

#define GCC_QUPV3_WRAP1_S5_CLK					113

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				114

#define GCC_QUPV3_WRAP2_CORE_2X_CLK				115

#define GCC_QUPV3_WRAP2_CORE_CLK				116

#define GCC_QUPV3_WRAP2_S0_CLK					117

#define GCC_QUPV3_WRAP2_S0_CLK_SRC				118

#define GCC_QUPV3_WRAP2_S1_CLK					119

#define GCC_QUPV3_WRAP2_S1_CLK_SRC				120

#define GCC_QUPV3_WRAP2_S2_CLK					121

#define GCC_QUPV3_WRAP2_S2_CLK_SRC				122

#define GCC_QUPV3_WRAP2_S3_CLK					123

#define GCC_QUPV3_WRAP2_S3_CLK_SRC				124

#define GCC_QUPV3_WRAP2_S4_CLK					125

#define GCC_QUPV3_WRAP2_S4_CLK_SRC				126

#define GCC_QUPV3_WRAP2_S5_CLK					127

#define GCC_QUPV3_WRAP2_S5_CLK_SRC				128

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				129

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				130

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				131

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				132

#define GCC_QUPV3_WRAP_2_M_AHB_CLK				133

#define GCC_QUPV3_WRAP_2_S_AHB_CLK				134

#define GCC_SDCC2_AHB_CLK					135

#define GCC_SDCC2_APPS_CLK					136

#define GCC_SDCC2_APPS_CLK_SRC					137

#define GCC_SDCC4_AHB_CLK					138

#define GCC_SDCC4_APPS_CLK					139

#define GCC_SDCC4_APPS_CLK_SRC					140

#define GCC_SYS_NOC_CPUSS_AHB_CLK				141

#define GCC_TSIF_AHB_CLK					142

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				143

#define GCC_TSIF_REF_CLK					144

#define GCC_TSIF_REF_CLK_SRC					145

#define GCC_UFS_CARD_AHB_CLK					146

#define GCC_UFS_CARD_AXI_CLK					147

#define GCC_UFS_CARD_AXI_CLK_SRC				148

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				149

#define GCC_UFS_CARD_CLKREF_CLK					150

#define GCC_UFS_CARD_ICE_CORE_CLK				151

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				152

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			153

#define GCC_UFS_CARD_PHY_AUX_CLK				154

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				155

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				156

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				157

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				158

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				159

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				160

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			161

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			162

#define GCC_UFS_MEM_CLKREF_CLK					163

#define GCC_UFS_PHY_AHB_CLK					164

#define GCC_UFS_PHY_AXI_CLK					165

#define GCC_UFS_PHY_AXI_CLK_SRC					166

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				167

#define GCC_UFS_PHY_ICE_CORE_CLK				168

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				169

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				170

#define GCC_UFS_PHY_PHY_AUX_CLK					171

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				172

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				173

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				174

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				175

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				176

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				177

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				178

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			179

#define GCC_USB30_PRIM_MASTER_CLK				180

#define GCC_USB30_PRIM_MASTER_CLK_SRC				181

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				182

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			183

#define GCC_USB30_PRIM_SLEEP_CLK				184

#define GCC_USB30_SEC_MASTER_CLK				185

#define GCC_USB30_SEC_MASTER_CLK_SRC				186

#define GCC_USB30_SEC_MOCK_UTMI_CLK				187

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				188

#define GCC_USB30_SEC_SLEEP_CLK					189

#define GCC_USB3_PRIM_CLKREF_CLK				190

#define GCC_USB3_PRIM_PHY_AUX_CLK				191

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				192

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				193

#define GCC_USB3_PRIM_PHY_PIPE_CLK				194

#define GCC_USB3_SEC_CLKREF_CLK					195

#define GCC_USB3_SEC_PHY_AUX_CLK				196

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				197

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				198

#define GCC_USB3_SEC_PHY_PIPE_CLK				199

#define GCC_VIDEO_AHB_CLK					200

#define GCC_VIDEO_AXI0_CLK					201

#define GCC_VIDEO_AXI1_CLK					202

#define GCC_VIDEO_AXIC_CLK					203

#define GCC_VIDEO_XO_CLK					204

#define GPLL0							205

#define GPLL0_OUT_EVEN						206

#define GPLL1							207

#define GPLL4							208

#define GPLL7							209

#define GPLL9							210

#define GCC_QUPV3_WRAP0_S0_CLK					82

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				83

#define GCC_QUPV3_WRAP0_S1_CLK					84

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				85

#define GCC_QUPV3_WRAP0_S2_CLK					86

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				87

#define GCC_QUPV3_WRAP0_S3_CLK					88

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				89

#define GCC_QUPV3_WRAP0_S4_CLK					90

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				91

#define GCC_QUPV3_WRAP0_S5_CLK					92

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				93

#define GCC_QUPV3_WRAP0_S6_CLK					94

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				95

#define GCC_QUPV3_WRAP0_S7_CLK					96

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				97

#define GCC_QUPV3_WRAP1_S0_CLK					98

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				99

#define GCC_QUPV3_WRAP1_S1_CLK					100

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				101

#define GCC_QUPV3_WRAP1_S2_CLK					102

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				103

#define GCC_QUPV3_WRAP1_S3_CLK					104

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				105

#define GCC_QUPV3_WRAP1_S4_CLK					106

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				107

#define GCC_QUPV3_WRAP1_S5_CLK					108

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				109

#define GCC_QUPV3_WRAP2_S0_CLK					110

#define GCC_QUPV3_WRAP2_S0_CLK_SRC				111

#define GCC_QUPV3_WRAP2_S1_CLK					112

#define GCC_QUPV3_WRAP2_S1_CLK_SRC				113

#define GCC_QUPV3_WRAP2_S2_CLK					114

#define GCC_QUPV3_WRAP2_S2_CLK_SRC				115

#define GCC_QUPV3_WRAP2_S3_CLK					116

#define GCC_QUPV3_WRAP2_S3_CLK_SRC				117

#define GCC_QUPV3_WRAP2_S4_CLK					118

#define GCC_QUPV3_WRAP2_S4_CLK_SRC				119

#define GCC_QUPV3_WRAP2_S5_CLK					120

#define GCC_QUPV3_WRAP2_S5_CLK_SRC				121

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				122

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				123

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				124

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				125

#define GCC_QUPV3_WRAP_2_M_AHB_CLK				126

#define GCC_QUPV3_WRAP_2_S_AHB_CLK				127

#define GCC_SDCC2_AHB_CLK					128

#define GCC_SDCC2_APPS_CLK					129

#define GCC_SDCC2_APPS_CLK_SRC					130

#define GCC_SDCC4_AHB_CLK					131

#define GCC_SDCC4_APPS_CLK					132

#define GCC_SDCC4_APPS_CLK_SRC					133

#define GCC_SYS_NOC_CPUSS_AHB_CLK				134

#define GCC_TSIF_AHB_CLK					135

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				136

#define GCC_TSIF_REF_CLK					137

#define GCC_TSIF_REF_CLK_SRC					138

#define GCC_UFS_CARD_AHB_CLK					139

#define GCC_UFS_CARD_AXI_CLK					140

#define GCC_UFS_CARD_AXI_CLK_SRC				141

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				142

#define GCC_UFS_CARD_CLKREF_CLK					143

#define GCC_UFS_CARD_ICE_CORE_CLK				144

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				145

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			146

#define GCC_UFS_CARD_PHY_AUX_CLK				147

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				148

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				149

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				150

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				151

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				152

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				153

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			154

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			155

#define GCC_UFS_MEM_CLKREF_CLK					156

#define GCC_UFS_PHY_AHB_CLK					157

#define GCC_UFS_PHY_AXI_CLK					158

#define GCC_UFS_PHY_AXI_CLK_SRC					159

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				160

#define GCC_UFS_PHY_ICE_CORE_CLK				161

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				162

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				163

#define GCC_UFS_PHY_PHY_AUX_CLK					164

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				165

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				166

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				167

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				168

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				169

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				170

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				171

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			172

#define GCC_USB30_PRIM_MASTER_CLK				173

#define GCC_USB30_PRIM_MASTER_CLK_SRC				174

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				175

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			176

#define GCC_USB30_PRIM_SLEEP_CLK				177

#define GCC_USB30_SEC_MASTER_CLK				178

#define GCC_USB30_SEC_MASTER_CLK_SRC				179

#define GCC_USB30_SEC_MOCK_UTMI_CLK				180

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				181

#define GCC_USB30_SEC_SLEEP_CLK					182

#define GCC_USB3_PRIM_CLKREF_CLK				183

#define GCC_USB3_PRIM_PHY_AUX_CLK				184

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				185

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				186

#define GCC_USB3_PRIM_PHY_PIPE_CLK				187

#define GCC_USB3_SEC_CLKREF_CLK					188

#define GCC_USB3_SEC_PHY_AUX_CLK				189

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				190

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				191

#define GCC_USB3_SEC_PHY_PIPE_CLK				192

#define GCC_VIDEO_AHB_CLK					193

#define GCC_VIDEO_AXI0_CLK					194

#define GCC_VIDEO_AXI1_CLK					195

#define GCC_VIDEO_AXIC_CLK					196

#define GCC_VIDEO_XO_CLK					197

#define GPLL0							198

#define GPLL0_OUT_EVEN						199

#define GPLL1							200

#define GPLL4							201

#define GPLL7							202

#define GPLL9							203



/* Reset clocks */

#define GCC_EMAC_BCR						0