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Commit 32c9ef99 authored by Bob Moore's avatar Bob Moore Committed by Len Brown
Browse files

ACPICA: Add function to handle PM1 control registers 



Added acpi_hw_write_pm1_control. This function writes both of the PM1
control registers (A/B). These registers are different than than
the PM1 A/B status and enable registers in that different values
can be written to the A/B registers.  Most notably, the SLP_TYP
bits can be different, as per the values returned from the _Sx
predefined methods.

Signed-off-by: default avatarBob Moore <robert.moore@intel.com>
Signed-off-by: default avatarLin Ming <ming.m.lin@intel.com>
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent 82d79b86

drivers/acpi/acpica/achware.h

+3 −2
Original line number Diff line number Diff line
@@ -64,8 +64,9 @@ u32 acpi_hw_get_mode(void); 
 */

struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id);



acpi_status

acpi_hw_register_read(u32 register_id, u32 * return_value);

acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control);



acpi_status acpi_hw_register_read(u32 register_id, u32 *return_value);



acpi_status acpi_hw_register_write(u32 register_id, u32 value);

drivers/acpi/acpica/aclocal.h

+4 −6
Original line number Diff line number Diff line
@@ -781,12 +781,10 @@ struct acpi_bit_register_info { 
#define ACPI_REGISTER_PM1_STATUS                0x01

#define ACPI_REGISTER_PM1_ENABLE                0x02

#define ACPI_REGISTER_PM1_CONTROL               0x03

#define ACPI_REGISTER_PM1A_CONTROL              0x04

#define ACPI_REGISTER_PM1B_CONTROL              0x05

#define ACPI_REGISTER_PM2_CONTROL               0x06

#define ACPI_REGISTER_PM_TIMER                  0x07

#define ACPI_REGISTER_PROCESSOR_BLOCK           0x08

#define ACPI_REGISTER_SMI_COMMAND_BLOCK         0x09

#define ACPI_REGISTER_PM2_CONTROL               0x04

#define ACPI_REGISTER_PM_TIMER                  0x05

#define ACPI_REGISTER_PROCESSOR_BLOCK           0x06

#define ACPI_REGISTER_SMI_COMMAND_BLOCK         0x07



/* Masks used to access the bit_registers */

drivers/acpi/acpica/hwregs.c

+36 −10
Original line number Diff line number Diff line
@@ -129,6 +129,42 @@ struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id) 
	return (&acpi_gbl_bit_register_info[register_id]);

}



/******************************************************************************

 *

 * FUNCTION:    acpi_hw_write_pm1_control

 *

 * PARAMETERS:  pm1a_control        - Value to be written to PM1A control

 *              pm1b_control        - Value to be written to PM1B control

 *

 * RETURN:      Status

 *

 * DESCRIPTION: Write the PM1 A/B control registers. These registers are

 *              different than than the PM1 A/B status and enable registers

 *              in that different values can be written to the A/B registers.

 *              Most notably, the SLP_TYP bits can be different, as per the

 *              values returned from the _Sx predefined methods.

 *

 ******************************************************************************/



acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control)

{

	acpi_status status;



	ACPI_FUNCTION_TRACE(hw_write_pm1_control);



	status = acpi_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block);

	if (ACPI_FAILURE(status)) {

		return_ACPI_STATUS(status);

	}



	if (acpi_gbl_FADT.xpm1b_control_block.address) {

		status =

		    acpi_write(pm1b_control,

			       &acpi_gbl_FADT.xpm1b_control_block);

	}

	return_ACPI_STATUS(status);

}



/******************************************************************************

 *

 * FUNCTION:    acpi_hw_register_read
@@ -295,16 +331,6 @@ acpi_status acpi_hw_register_write(u32 register_id, u32 value) 
						xpm1b_control_block);

		break;



	case ACPI_REGISTER_PM1A_CONTROL:	/* 16-bit access */



		status = acpi_write(value, &acpi_gbl_FADT.xpm1a_control_block);

		break;



	case ACPI_REGISTER_PM1B_CONTROL:	/* 16-bit access */



		status = acpi_write(value, &acpi_gbl_FADT.xpm1b_control_block);

		break;



	case ACPI_REGISTER_PM2_CONTROL:	/* 8-bit access */



		status = acpi_write(value, &acpi_gbl_FADT.xpm2_control_block);

drivers/acpi/acpica/hwsleep.c

+35 −49
Original line number Diff line number Diff line
@@ -147,9 +147,8 @@ acpi_status acpi_enter_sleep_state_prep(u8 sleep_state) 


	ACPI_FUNCTION_TRACE(acpi_enter_sleep_state_prep);



	/*

	 * _PSW methods could be run here to enable wake-on keyboard, LAN, etc.

	 */

	/* _PSW methods could be run here to enable wake-on keyboard, LAN, etc. */



	status = acpi_get_sleep_type_data(sleep_state,

					  &acpi_gbl_sleep_type_a,

					  &acpi_gbl_sleep_type_b);
@@ -223,8 +222,8 @@ ACPI_EXPORT_SYMBOL(acpi_enter_sleep_state_prep) 
 ******************************************************************************/

acpi_status asmlinkage acpi_enter_sleep_state(u8 sleep_state)

{

	u32 PM1Acontrol;

	u32 PM1Bcontrol;

	u32 pm1a_control;

	u32 pm1b_control;

	struct acpi_bit_register_info *sleep_type_reg_info;

	struct acpi_bit_register_info *sleep_enable_reg_info;

	u32 in_value;
@@ -289,24 +288,25 @@ acpi_status asmlinkage acpi_enter_sleep_state(u8 sleep_state) 


	/* Get current value of PM1A control */



	status = acpi_hw_register_read(ACPI_REGISTER_PM1_CONTROL, &PM1Acontrol);

	status = acpi_hw_register_read(ACPI_REGISTER_PM1_CONTROL,

				       &pm1a_control);

	if (ACPI_FAILURE(status)) {

		return_ACPI_STATUS(status);

	}

	ACPI_DEBUG_PRINT((ACPI_DB_INIT,

			  "Entering sleep state [S%d]\n", sleep_state));



	/* Clear SLP_EN and SLP_TYP fields */

	/* Clear the SLP_EN and SLP_TYP fields */



	PM1Acontrol &= ~(sleep_type_reg_info->access_bit_mask |

	pm1a_control &= ~(sleep_type_reg_info->access_bit_mask |

			  sleep_enable_reg_info->access_bit_mask);

	PM1Bcontrol = PM1Acontrol;

	pm1b_control = pm1a_control;



	/* Insert SLP_TYP bits */

	/* Insert the SLP_TYP bits */



	PM1Acontrol |=

	pm1a_control |=

	    (acpi_gbl_sleep_type_a << sleep_type_reg_info->bit_position);

	PM1Bcontrol |=

	pm1b_control |=

	    (acpi_gbl_sleep_type_b << sleep_type_reg_info->bit_position);



	/*
@@ -314,37 +314,25 @@ acpi_status asmlinkage acpi_enter_sleep_state(u8 sleep_state) 
	 * poorly implemented hardware.

	 */



	/* Write #1: fill in SLP_TYP data */

	/* Write #1: write the SLP_TYP data to the PM1 Control registers */



	status = acpi_hw_register_write(ACPI_REGISTER_PM1A_CONTROL,

					PM1Acontrol);

	status = acpi_hw_write_pm1_control(pm1a_control, pm1b_control);

	if (ACPI_FAILURE(status)) {

		return_ACPI_STATUS(status);

	}



	status = acpi_hw_register_write(ACPI_REGISTER_PM1B_CONTROL,

					PM1Bcontrol);

	if (ACPI_FAILURE(status)) {

		return_ACPI_STATUS(status);

	}



	/* Insert SLP_ENABLE bit */

	/* Insert the sleep enable (SLP_EN) bit */



	PM1Acontrol |= sleep_enable_reg_info->access_bit_mask;

	PM1Bcontrol |= sleep_enable_reg_info->access_bit_mask;

	pm1a_control |= sleep_enable_reg_info->access_bit_mask;

	pm1b_control |= sleep_enable_reg_info->access_bit_mask;



	/* Write #2: SLP_TYP + SLP_EN */

	/* Flush caches, as per ACPI specification */



	ACPI_FLUSH_CPU_CACHE();



	status = acpi_hw_register_write(ACPI_REGISTER_PM1A_CONTROL,

					PM1Acontrol);

	if (ACPI_FAILURE(status)) {

		return_ACPI_STATUS(status);

	}

	/* Write #2: Write both SLP_TYP + SLP_EN */



	status = acpi_hw_register_write(ACPI_REGISTER_PM1B_CONTROL,

					PM1Bcontrol);

	status = acpi_hw_write_pm1_control(pm1a_control, pm1b_control);

	if (ACPI_FAILURE(status)) {

		return_ACPI_STATUS(status);

	}
@@ -471,8 +459,8 @@ acpi_status acpi_leave_sleep_state_prep(u8 sleep_state) 
	acpi_status status;

	struct acpi_bit_register_info *sleep_type_reg_info;

	struct acpi_bit_register_info *sleep_enable_reg_info;

	u32 PM1Acontrol;

	u32 PM1Bcontrol;

	u32 pm1a_control;

	u32 pm1b_control;



	ACPI_FUNCTION_TRACE(acpi_leave_sleep_state_prep);
@@ -493,31 +481,29 @@ acpi_status acpi_leave_sleep_state_prep(u8 sleep_state) 
		/* Get current value of PM1A control */



		status = acpi_hw_register_read(ACPI_REGISTER_PM1_CONTROL,

					       &PM1Acontrol);

					       &pm1a_control);

		if (ACPI_SUCCESS(status)) {



			/* Clear SLP_EN and SLP_TYP fields */

			/* Clear the SLP_EN and SLP_TYP fields */



			PM1Acontrol &= ~(sleep_type_reg_info->access_bit_mask |

			pm1a_control &= ~(sleep_type_reg_info->access_bit_mask |

					  sleep_enable_reg_info->

					  access_bit_mask);

			PM1Bcontrol = PM1Acontrol;

			pm1b_control = pm1a_control;



			/* Insert SLP_TYP bits */

			/* Insert the SLP_TYP bits */



			PM1Acontrol |=

			pm1a_control |=

			    (acpi_gbl_sleep_type_a << sleep_type_reg_info->

			     bit_position);

			PM1Bcontrol |=

			pm1b_control |=

			    (acpi_gbl_sleep_type_b << sleep_type_reg_info->

			     bit_position);



			/* Just ignore any errors */

			/* Write the control registers and ignore any errors */



			(void)acpi_hw_register_write(ACPI_REGISTER_PM1A_CONTROL,

						     PM1Acontrol);

			(void)acpi_hw_register_write(ACPI_REGISTER_PM1B_CONTROL,

						     PM1Bcontrol);

			(void)acpi_hw_write_pm1_control(pm1a_control,

							pm1b_control);

		}

	}