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Commit 313a025f authored by Jordan Crouse's avatar Jordan Crouse Committed by Mohammed Mirza Mandayappurath Manzoor
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msm: kgsl: Try to improve coresight register accesses



Instead of having if / else statements scattered throughout the
coresight driver to access GX or CX register banks use function
hooks in the target specific coresight structs. This helps
streamline the code and cut down on the decision points at the
cost of just a bit more infrastructure on the target side.

Change-Id: Ic0dedbada9d1632d220d0dfb186ccd0adff6be91
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 2364d180
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+12 −4
Original line number Original line Diff line number Diff line
@@ -868,16 +868,24 @@ ssize_t adreno_coresight_store_register(struct device *dev,


/**
/**
 * struct adreno_coresight - GPU specific coresight definition
 * struct adreno_coresight - GPU specific coresight definition
 * @registers - Array of GPU specific registers to configure trace bus output
 * @registers: Array of GPU specific registers to configure trace bus output
 * @count - Number of registers in the array
 * @count: Number of registers in the array
 * @groups - Pointer to an attribute list of control files
 * @groups: Pointer to an attribute list of control files
 * @atid - The unique ATID value of the coresight device
 * @atid: The unique ATID value of the coresight device
 * @read: a function pointer to the appropriate register read function for this
 * device
 * @write: a function pointer to the appropriate register write function for
 * this device
 */
 */
struct adreno_coresight {
struct adreno_coresight {
	struct adreno_coresight_register *registers;
	struct adreno_coresight_register *registers;
	unsigned int count;
	unsigned int count;
	const struct attribute_group **groups;
	const struct attribute_group **groups;
	unsigned int atid;
	unsigned int atid;
	void (*read)(struct kgsl_device *device,
		unsigned int offsetwords, unsigned int *value);
	void (*write)(struct kgsl_device *device,
		unsigned int offsetwords, unsigned int value);
};
};




+2 −0
Original line number Original line Diff line number Diff line
@@ -1467,6 +1467,8 @@ static struct adreno_coresight a3xx_coresight = {
	.registers = a3xx_coresight_registers,
	.registers = a3xx_coresight_registers,
	.count = ARRAY_SIZE(a3xx_coresight_registers),
	.count = ARRAY_SIZE(a3xx_coresight_registers),
	.groups = a3xx_coresight_groups,
	.groups = a3xx_coresight_groups,
	.read = kgsl_regread,
	.write = kgsl_regwrite,
};
};


static unsigned int a3xx_int_bits[ADRENO_INT_BITS_MAX] = {
static unsigned int a3xx_int_bits[ADRENO_INT_BITS_MAX] = {
+2 −0
Original line number Original line Diff line number Diff line
@@ -1680,6 +1680,8 @@ static struct adreno_coresight a4xx_coresight = {
	.registers = a4xx_coresight_registers,
	.registers = a4xx_coresight_registers,
	.count = ARRAY_SIZE(a4xx_coresight_registers),
	.count = ARRAY_SIZE(a4xx_coresight_registers),
	.groups = a4xx_coresight_groups,
	.groups = a4xx_coresight_groups,
	.read = kgsl_regread,
	.write = kgsl_regwrite,
};
};


static void a4xx_preempt_callback(struct adreno_device *adreno_dev, int bit)
static void a4xx_preempt_callback(struct adreno_device *adreno_dev, int bit)
+2 −0
Original line number Original line Diff line number Diff line
@@ -3596,6 +3596,8 @@ static struct adreno_coresight a5xx_coresight = {
	.registers = a5xx_coresight_registers,
	.registers = a5xx_coresight_registers,
	.count = ARRAY_SIZE(a5xx_coresight_registers),
	.count = ARRAY_SIZE(a5xx_coresight_registers),
	.groups = a5xx_coresight_groups,
	.groups = a5xx_coresight_groups,
	.read = kgsl_regread,
	.write = kgsl_regwrite,
};
};


struct adreno_gpudev adreno_a5xx_gpudev = {
struct adreno_gpudev adreno_a5xx_gpudev = {
+4 −0
Original line number Original line Diff line number Diff line
@@ -2190,12 +2190,16 @@ static struct adreno_coresight a6xx_coresight = {
	.registers = a6xx_coresight_regs,
	.registers = a6xx_coresight_regs,
	.count = ARRAY_SIZE(a6xx_coresight_regs),
	.count = ARRAY_SIZE(a6xx_coresight_regs),
	.groups = a6xx_coresight_groups,
	.groups = a6xx_coresight_groups,
	.read = kgsl_regread,
	.write = kgsl_regwrite,
};
};


static struct adreno_coresight a6xx_coresight_cx = {
static struct adreno_coresight a6xx_coresight_cx = {
	.registers = a6xx_coresight_regs_cx,
	.registers = a6xx_coresight_regs_cx,
	.count = ARRAY_SIZE(a6xx_coresight_regs_cx),
	.count = ARRAY_SIZE(a6xx_coresight_regs_cx),
	.groups = a6xx_coresight_groups_cx,
	.groups = a6xx_coresight_groups_cx,
	.read = adreno_cx_dbgc_regread,
	.write = adreno_cx_dbgc_regwrite,
};
};


static struct adreno_perfcount_register a6xx_perfcounters_cp[] = {
static struct adreno_perfcount_register a6xx_perfcounters_cp[] = {
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