Loading Documentation/devicetree/bindings/arm/msm/qcom,osm.txt +3 −2 Original line number Diff line number Diff line Loading @@ -9,7 +9,7 @@ Properties: - compatible Usage: required Value type: <string> Definition: must be "qcom,clk-cpu-osm". Definition: must be "qcom,clk-cpu-osm" or "qcom,clk-cpu-osm-sdmshrike". - reg Usage: required Loading @@ -20,7 +20,8 @@ Properties: Usage: required Value type: <stringlist> Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base", and "osm_perfpcl_base". and "osm_perfcl_base". Can optionally have "osm_perfpcl_base". Must be specified in the same order as the corresponding addresses are specified in the reg property. Loading drivers/clk/qcom/clk-cpu-osm.c +47 −10 Original line number Diff line number Diff line Loading @@ -80,6 +80,8 @@ struct clk_osm { unsigned long rate; }; static bool is_sdmshrike; static inline struct clk_osm *to_clk_osm(struct clk_hw *_hw) { return container_of(_hw, struct clk_osm, hw); Loading Loading @@ -394,6 +396,18 @@ static struct clk_osm cpu6_perfcl_clk = { }, }; static struct clk_osm cpu7_perfcl_clk = { .core_num = 3, .total_cycle_counter = 0, .prev_cycle_counter = 0, .hw.init = &(struct clk_init_data){ .name = "cpu7_perfcl_clk", .parent_names = (const char *[]){ "perfcl_clk" }, .num_parents = 1, .ops = &clk_ops_core, }, }; static struct clk_osm perfpcl_clk = { .cluster_num = 3, .hw.init = &osm_clks_init[3], Loading Loading @@ -427,14 +441,9 @@ static struct clk_hw *osm_qcom_clk_hws[] = { [PERFCL_CLK] = &perfcl_clk.hw, [CPU7_PERFPCL_CLK] = &cpu7_perfpcl_clk.hw, [PERFPCL_CLK] = &perfpcl_clk.hw, [CPU7_PERFCL_CLK] = NULL, }; static struct clk_osm *logical_cpu_to_clk(int cpu) { struct device_node *cpu_node; const u32 *cell; u64 hwid; static struct clk_osm *cpu_clk_map[NR_CPUS]; struct clk_osm *clk_cpu_map[] = { &cpu0_pwrcl_clk, &cpu1_pwrcl_clk, Loading @@ -446,6 +455,13 @@ static struct clk_osm *logical_cpu_to_clk(int cpu) &cpu7_perfpcl_clk, }; static struct clk_osm *logical_cpu_to_clk(int cpu) { struct device_node *cpu_node; const u32 *cell; u64 hwid; static struct clk_osm *cpu_clk_map[NR_CPUS]; if (!cpu_clk_map[cpu]) { cpu_node = of_get_cpu_node(cpu, NULL); if (!cpu_node) Loading Loading @@ -959,6 +975,9 @@ static int clk_osm_resources_init(struct platform_device *pdev) return -ENOMEM; } if (is_sdmshrike) return 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "osm_perfpcl_base"); if (!res) { Loading @@ -979,6 +998,15 @@ static int clk_osm_resources_init(struct platform_device *pdev) return 0; } static void clk_cpu_osm_driver_sdmshrike_fixup(void) { osm_qcom_clk_hws[CPU7_PERFPCL_CLK] = NULL; osm_qcom_clk_hws[PERFPCL_CLK] = NULL; osm_qcom_clk_hws[CPU7_PERFCL_CLK] = &cpu7_perfcl_clk.hw; clk_cpu_map[7] = &cpu7_perfcl_clk; } static int clk_cpu_osm_driver_probe(struct platform_device *pdev) { int rc = 0, i; Loading @@ -990,6 +1018,11 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) .get_cpu_cycle_counter = clk_osm_get_cpu_cycle_counter, }; is_sdmshrike = of_device_is_compatible(pdev->dev.of_node, "qcom,clk-cpu-osm-sdmshrike"); if (is_sdmshrike) clk_cpu_osm_driver_sdmshrike_fixup(); clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data), GFP_KERNEL); if (!clk_data) Loading Loading @@ -1054,6 +1087,9 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) /* Register OSM l3, pwr and perf clocks with Clock Framework */ for (i = 0; i < num_clks; i++) { if (!osm_qcom_clk_hws[i]) continue; clk = devm_clk_register(&pdev->dev, osm_qcom_clk_hws[i]); if (IS_ERR(clk)) { dev_err(&pdev->dev, "Unable to register CPU clock at index %d\n", Loading Loading @@ -1105,6 +1141,7 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) static const struct of_device_id match_table[] = { { .compatible = "qcom,clk-cpu-osm" }, { .compatible = "qcom,clk-cpu-osm-sdmshrike" }, {} }; Loading include/dt-bindings/clock/qcom,cpucc-sdm855.h +2 −1 Original line number Diff line number Diff line /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -29,5 +29,6 @@ #define PERFCL_CLK 12 #define CPU7_PERFPCL_CLK 13 #define PERFPCL_CLK 14 #define CPU7_PERFCL_CLK 15 #endif Loading
Documentation/devicetree/bindings/arm/msm/qcom,osm.txt +3 −2 Original line number Diff line number Diff line Loading @@ -9,7 +9,7 @@ Properties: - compatible Usage: required Value type: <string> Definition: must be "qcom,clk-cpu-osm". Definition: must be "qcom,clk-cpu-osm" or "qcom,clk-cpu-osm-sdmshrike". - reg Usage: required Loading @@ -20,7 +20,8 @@ Properties: Usage: required Value type: <stringlist> Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base", and "osm_perfpcl_base". and "osm_perfcl_base". Can optionally have "osm_perfpcl_base". Must be specified in the same order as the corresponding addresses are specified in the reg property. Loading
drivers/clk/qcom/clk-cpu-osm.c +47 −10 Original line number Diff line number Diff line Loading @@ -80,6 +80,8 @@ struct clk_osm { unsigned long rate; }; static bool is_sdmshrike; static inline struct clk_osm *to_clk_osm(struct clk_hw *_hw) { return container_of(_hw, struct clk_osm, hw); Loading Loading @@ -394,6 +396,18 @@ static struct clk_osm cpu6_perfcl_clk = { }, }; static struct clk_osm cpu7_perfcl_clk = { .core_num = 3, .total_cycle_counter = 0, .prev_cycle_counter = 0, .hw.init = &(struct clk_init_data){ .name = "cpu7_perfcl_clk", .parent_names = (const char *[]){ "perfcl_clk" }, .num_parents = 1, .ops = &clk_ops_core, }, }; static struct clk_osm perfpcl_clk = { .cluster_num = 3, .hw.init = &osm_clks_init[3], Loading Loading @@ -427,14 +441,9 @@ static struct clk_hw *osm_qcom_clk_hws[] = { [PERFCL_CLK] = &perfcl_clk.hw, [CPU7_PERFPCL_CLK] = &cpu7_perfpcl_clk.hw, [PERFPCL_CLK] = &perfpcl_clk.hw, [CPU7_PERFCL_CLK] = NULL, }; static struct clk_osm *logical_cpu_to_clk(int cpu) { struct device_node *cpu_node; const u32 *cell; u64 hwid; static struct clk_osm *cpu_clk_map[NR_CPUS]; struct clk_osm *clk_cpu_map[] = { &cpu0_pwrcl_clk, &cpu1_pwrcl_clk, Loading @@ -446,6 +455,13 @@ static struct clk_osm *logical_cpu_to_clk(int cpu) &cpu7_perfpcl_clk, }; static struct clk_osm *logical_cpu_to_clk(int cpu) { struct device_node *cpu_node; const u32 *cell; u64 hwid; static struct clk_osm *cpu_clk_map[NR_CPUS]; if (!cpu_clk_map[cpu]) { cpu_node = of_get_cpu_node(cpu, NULL); if (!cpu_node) Loading Loading @@ -959,6 +975,9 @@ static int clk_osm_resources_init(struct platform_device *pdev) return -ENOMEM; } if (is_sdmshrike) return 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "osm_perfpcl_base"); if (!res) { Loading @@ -979,6 +998,15 @@ static int clk_osm_resources_init(struct platform_device *pdev) return 0; } static void clk_cpu_osm_driver_sdmshrike_fixup(void) { osm_qcom_clk_hws[CPU7_PERFPCL_CLK] = NULL; osm_qcom_clk_hws[PERFPCL_CLK] = NULL; osm_qcom_clk_hws[CPU7_PERFCL_CLK] = &cpu7_perfcl_clk.hw; clk_cpu_map[7] = &cpu7_perfcl_clk; } static int clk_cpu_osm_driver_probe(struct platform_device *pdev) { int rc = 0, i; Loading @@ -990,6 +1018,11 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) .get_cpu_cycle_counter = clk_osm_get_cpu_cycle_counter, }; is_sdmshrike = of_device_is_compatible(pdev->dev.of_node, "qcom,clk-cpu-osm-sdmshrike"); if (is_sdmshrike) clk_cpu_osm_driver_sdmshrike_fixup(); clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data), GFP_KERNEL); if (!clk_data) Loading Loading @@ -1054,6 +1087,9 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) /* Register OSM l3, pwr and perf clocks with Clock Framework */ for (i = 0; i < num_clks; i++) { if (!osm_qcom_clk_hws[i]) continue; clk = devm_clk_register(&pdev->dev, osm_qcom_clk_hws[i]); if (IS_ERR(clk)) { dev_err(&pdev->dev, "Unable to register CPU clock at index %d\n", Loading Loading @@ -1105,6 +1141,7 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) static const struct of_device_id match_table[] = { { .compatible = "qcom,clk-cpu-osm" }, { .compatible = "qcom,clk-cpu-osm-sdmshrike" }, {} }; Loading
include/dt-bindings/clock/qcom,cpucc-sdm855.h +2 −1 Original line number Diff line number Diff line /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -29,5 +29,6 @@ #define PERFCL_CLK 12 #define CPU7_PERFPCL_CLK 13 #define PERFPCL_CLK 14 #define CPU7_PERFCL_CLK 15 #endif