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Commit 3106dba6 authored by Neil Armstrong's avatar Neil Armstrong Committed by Andy Gross
Browse files

ARM: dts: Add Sierra Wireless WP8548 dtsi 



In order to support the Sierra Wireless WP8548 module based on the
Qualcomm MDM9615 SoC, add a dtsi file.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent c93972df

arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi

0 → 100644
+170 −0
Original line number Diff line number Diff line 
/*

 * Device Tree Source for Sierra Wireless WP8548 Module

 *

 * Copyright (C) 2016 BayLibre, SAS.

 * Author : Neil Armstrong <narmstrong@baylibre.com>

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual

 * licensing only applies to this file, and not this project as a

 * whole.

 *

 *  a) This file is free software; you can redistribute it and/or

 *     modify it under the terms of the GNU General Public License as

 *     published by the Free Software Foundation; either version 2 of the

 *     License, or (at your option) any later version.

 *

 *     This file is distributed in the hope that it will be useful,

 *     but WITHOUT ANY WARRANTY; without even the implied warranty of

 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *     GNU General Public License for more details.

 *

 * Or, alternatively,

 *

 *  b) Permission is hereby granted, free of charge, to any person

 *     obtaining a copy of this software and associated documentation

 *     files (the "Software"), to deal in the Software without

 *     restriction, including without limitation the rights to use,

 *     copy, modify, merge, publish, distribute, sublicense, and/or

 *     sell copies of the Software, and to permit persons to whom the

 *     Software is furnished to do so, subject to the following

 *     conditions:

 *

 *     The above copyright notice and this permission notice shall be

 *     included in all copies or substantial portions of the Software.

 *

 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES

 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 *     OTHER DEALINGS IN THE SOFTWARE.

 */



#include "qcom-mdm9615.dtsi"



/ {

	model = "Sierra Wireless WP8548 Module";

	compatible = "swir,wp8548", "qcom,mdm9615";



	memory {

		reg = <0x48000000 0x7F00000>;

	};

};



&msmgpio {

	pinctrl-0 = <&reset_out_pins>;

	pinctrl-names = "default";



	gsbi3_pins: gsbi3_pins {

		mux {

			pins = "gpio8", "gpio9", "gpio10", "gpio11";

			function = "gsbi3";

			drive-strength = <8>;

			bias-disable;

		};

	};



	gsbi4_pins: gsbi4_pins {

		mux {

			pins = "gpio12", "gpio13", "gpio14", "gpio15";

			function = "gsbi4";

			drive-strength = <8>;

			bias-disable;

		};

	};



	gsbi5_i2c_pins: gsbi5_i2c_pins {

		pin16 {

			pins = "gpio16";

			function = "gsbi5_i2c";

			drive-strength = <8>;

			bias-disable;

		};



		pin17 {

			pins = "gpio17";

			function = "gsbi5_i2c";

			drive-strength = <2>;

			bias-disable;

		};

	};



	gsbi5_uart_pins: gsbi5_uart_pins {

		mux {

			pins = "gpio18", "gpio19";

			function = "gsbi5_uart";

			drive-strength = <8>;

			bias-disable;

		};

	};



	reset_out_pins: reset_out_pins {

		pins {

			pins = "gpio66";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-up;

			output-high;

		};

	};

};



&pmicgpio {

	usb_vbus_5v_pins: usb_vbus_5v_pins {

		pins = "gpio4";

		function = "normal";

		output-high;

		bias-disable;

		qcom,drive-strength = <1>;

		power-source = <2>;

	};

};



&gsbi3 {

	status = "ok";

	qcom,mode = <GSBI_PROT_SPI>;

};



&gsbi3_spi {

	status = "ok";

	pinctrl-0 = <&gsbi3_pins>;

	pinctrl-names = "default";

	assigned-clocks = <&gcc GSBI3_QUP_CLK>;

	assigned-clock-rates = <24000000>;

};



&gsbi4 {

	status = "ok";

	qcom,mode = <GSBI_PROT_UART_W_FC>;

};



&gsbi4_serial {

	status = "ok";

	pinctrl-0 = <&gsbi4_pins>;

	pinctrl-names = "default";

};



&gsbi5 {

	status = "ok";

	qcom,mode = <GSBI_PROT_I2C_UART>;

};



&gsbi5_i2c {

	status = "ok";

	clock-frequency = <200000>;

	pinctrl-0 = <&gsbi5_i2c_pins>;

	pinctrl-names = "default";

};



&gsbi5_serial {

	status = "ok";

	pinctrl-0 = <&gsbi5_uart_pins>;

	pinctrl-names = "default";

};



&sdcc1 {

	status = "ok";

};