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Commit 30d84397 authored by Ben Shelton's avatar Ben Shelton Committed by Jeff Kirsher
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ice: Do not check INTEVENT bit for OICR interrupts 



According to the hardware spec, checking the INTEVENT bit isn't a
reliable way to detect if an OICR interrupt has occurred. This is
because this bit can be cleared by the hardware/firmware before the
interrupt service routine has run. So instead, just check for OICR
events every time.

Fixes: 940b61af ("ice: Initialize PF and setup miscellaneous interrupt")
Signed-off-by: default avatarBen Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: default avatarTony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 34357a90

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

+0 −2
Original line number Original line Diff line number Diff line
@@ -121,8 +121,6 @@ 
#define PFINT_FW_CTL_CAUSE_ENA_S	30

#define PFINT_FW_CTL_CAUSE_ENA_S	30

#define PFINT_FW_CTL_CAUSE_ENA_M	BIT(PFINT_FW_CTL_CAUSE_ENA_S)

#define PFINT_FW_CTL_CAUSE_ENA_M	BIT(PFINT_FW_CTL_CAUSE_ENA_S)

#define PFINT_OICR			0x0016CA00

#define PFINT_OICR			0x0016CA00

#define PFINT_OICR_INTEVENT_S		0

#define PFINT_OICR_INTEVENT_M		BIT(PFINT_OICR_INTEVENT_S)

#define PFINT_OICR_HLP_RDY_S		14

#define PFINT_OICR_HLP_RDY_S		14

#define PFINT_OICR_HLP_RDY_M		BIT(PFINT_OICR_HLP_RDY_S)

#define PFINT_OICR_HLP_RDY_M		BIT(PFINT_OICR_HLP_RDY_S)

#define PFINT_OICR_CPM_RDY_S		15

#define PFINT_OICR_CPM_RDY_S		15

drivers/net/ethernet/intel/ice/ice_main.c

+0 −4
Original line number Original line Diff line number Diff line
@@ -1722,9 +1722,6 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data) 
	oicr = rd32(hw, PFINT_OICR);

	oicr = rd32(hw, PFINT_OICR);

	ena_mask = rd32(hw, PFINT_OICR_ENA);

	ena_mask = rd32(hw, PFINT_OICR_ENA);





	if (!(oicr & PFINT_OICR_INTEVENT_M))

		goto ena_intr;



	if (oicr & PFINT_OICR_GRST_M) {

	if (oicr & PFINT_OICR_GRST_M) {

		u32 reset;

		u32 reset;

		/* we have a reset warning */

		/* we have a reset warning */
@@ -1782,7 +1779,6 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data) 
	}

	}

	ret = IRQ_HANDLED;

	ret = IRQ_HANDLED;





ena_intr:

	/* re-enable interrupt causes that are not handled during this pass */

	/* re-enable interrupt causes that are not handled during this pass */

	wr32(hw, PFINT_OICR_ENA, ena_mask);

	wr32(hw, PFINT_OICR_ENA, ena_mask);

	if (!test_bit(__ICE_DOWN, pf->state)) {

	if (!test_bit(__ICE_DOWN, pf->state)) {