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Commit 2f239783 authored by Jim Wang's avatar Jim Wang Committed by Gerrit - the friendly Code Review server
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clk: qcom: Update dispcc for sdmshirke_v2 2nd DP and eDP clocks 



Update dispcc for sdmshirke_v2, separate 2nd DP clock tree from
primary DP clocks, update eDP clock tree.

Change-Id: Ida3fce3603571d8c2b28c623e0921bfc1b64428a
Signed-off-by: default avatarJim Wang <jimwan@codeaurora.org>
parent 5c5b4128

drivers/clk/qcom/dispcc-sm8150.c

+116 −4
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -170,6 +170,26 @@ static const char * const disp_cc_parent_names_4[] = { 
	"core_bi_pll_test_se",

};



static const struct parent_map disp_cc_parent_map_4_sdmshrikev2[] = {

	{ P_BI_TCXO, 0 },

	{ P_EDP_PHY_PLL_LINK_CLK, 1 },

	{ P_EDP_PHY_PLL_VCO_DIV_CLK, 2 },

	{ P_DP_PHY_PLL_VCO_DIV_CLK, 3 },

	{ P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 },

	{ P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const disp_cc_parent_names_4_sdmshrikev2[] = {

	"bi_tcxo",

	"edp_phy_pll_link_clk",

	"edp_phy_pll_vco_div_clk",

	"dp_phy_pll_vco_div_clk",

	"dptx1_phy_pll_vco_div_clk",

	"dptx2_phy_pll_vco_div_clk",

	"core_bi_pll_test_se",

};



static const struct parent_map disp_cc_parent_map_5[] = {

	{ P_BI_TCXO, 0 },

	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
@@ -422,6 +442,15 @@ static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto1_clk_src[] = { 
	{ }

};



static const struct freq_tbl

ftbl_disp_cc_mdss_dp_crypto1_clk_src_sdmshrikev2[] = {

	F( 108000, P_DPTX1_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 180000, P_DPTX1_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 360000, P_DPTX1_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 540000, P_DPTX1_PHY_PLL_LINK_CLK,   3,   0,   0),

	{ }

};



static struct clk_rcg2 disp_cc_mdss_dp_crypto1_clk_src = {

	.cmd_rcgr = 0x2228,

	.mnd_width = 0,
@@ -444,6 +473,15 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto1_clk_src = { 
	},

};



static const struct freq_tbl

ftbl_disp_cc_mdss_dp_crypto_clk_src_sdmshrikev2[] = {

	F( 108000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 180000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 360000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 540000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	{ }

};



static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {

	.cmd_rcgr = 0x2194,

	.mnd_width = 0,
@@ -474,6 +512,16 @@ static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = { 
	{ }

};



static const struct freq_tbl

ftbl_disp_cc_mdss_dp_link1_clk_src_sdmshrikev2[] = {

	F( 19200, P_BI_TCXO, 1, 0, 0),

	F( 162000, P_DPTX1_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 270000, P_DPTX1_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 540000, P_DPTX1_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 810000, P_DPTX1_PHY_PLL_LINK_CLK,   1,   0,   0),

	{ }

};



static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {

	.cmd_rcgr = 0x220c,

	.mnd_width = 0,
@@ -496,6 +544,15 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { 
	},

};



static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src_sdmshrikev2[] = {

	F( 19200, P_BI_TCXO, 1, 0, 0),

	F( 162000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 270000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 540000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 810000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	{ }

};



static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {

	.cmd_rcgr = 0x2178,

	.mnd_width = 0,
@@ -624,6 +681,21 @@ static const struct freq_tbl ftbl_disp_cc_mdss_edp_link_clk_src[] = { 
	{ }

};



static const struct freq_tbl

ftbl_disp_cc_mdss_edp_link_clk_src_sdmshrikev2[] = {

	F( 19200, P_BI_TCXO, 1, 0, 0),

	F( 162000, P_EDP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 216000, P_EDP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 243000, P_EDP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 270000, P_EDP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 324000, P_EDP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 432000, P_EDP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 540000, P_EDP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 594000, P_EDP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 810000, P_EDP_PHY_PLL_LINK_CLK,   1,   0,   0),

	{ }

};



static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {

	.cmd_rcgr = 0x2270,

	.mnd_width = 0,
@@ -666,6 +738,20 @@ static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { 
	},

};



static struct clk_init_data disp_cc_mdss_edp_pixel_clk_src_sdmshrikev2 = {

	.name = "disp_cc_mdss_edp_pixel_clk_src",

	.parent_names = disp_cc_parent_names_4_sdmshrikev2,

	.num_parents = 7,

	.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

	.ops = &clk_dp_ops,

	.vdd_class = &vdd_mm,

	.num_rate_max = VDD_NUM,

	.rate_max = (unsigned long[VDD_NUM]) {

		[VDD_MIN] = 19200000,

		[VDD_LOWER] = 337500000,

		[VDD_LOW_L1] = 675000000},

};



static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {

	.cmd_rcgr = 0x2148,

	.mnd_width = 0,
@@ -1582,12 +1668,38 @@ static void disp_cc_sm8150_fixup_sdmshrikev2(struct regmap *regmap) 
{

	disp_cc_sm8150_fixup_sm8150v2(regmap);



	disp_cc_mdss_dp_crypto_clk_src.freq_tbl =

		ftbl_disp_cc_mdss_dp_crypto_clk_src_sdmshrikev2;

	disp_cc_mdss_dp_crypto1_clk_src.freq_tbl =

		ftbl_disp_cc_mdss_dp_crypto1_clk_src_sdmshrikev2;

	disp_cc_mdss_dp_link_clk_src.freq_tbl =

		ftbl_disp_cc_mdss_dp_link_clk_src_sdmshrikev2;

	disp_cc_mdss_dp_link1_clk_src.freq_tbl =

		ftbl_disp_cc_mdss_dp_link1_clk_src_sdmshrikev2;



	disp_cc_mdss_edp_link_clk_src.freq_tbl =

		ftbl_disp_cc_mdss_edp_link_clk_src_sdmshrikev2;

	disp_cc_mdss_edp_link_clk_src.clkr.hw.init->rate_max[VDD_MIN] =

		19200;

	disp_cc_mdss_edp_link_clk_src.clkr.hw.init->rate_max[VDD_LOWER] =

		270000;

	disp_cc_mdss_edp_link_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] =

		594000;

	disp_cc_mdss_edp_link_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] =

		810000;



	disp_cc_mdss_edp_pixel_clk_src.parent_map =

		disp_cc_parent_map_4_sdmshrikev2;

	disp_cc_mdss_edp_pixel_clk_src.clkr.hw.init =

		&disp_cc_mdss_edp_pixel_clk_src_sdmshrikev2;

	disp_cc_mdss_edp_pixel_clk_src.clkr.hw.init->rate_max[VDD_MIN] =

		19200;

	disp_cc_mdss_edp_pixel_clk_src.clkr.hw.init->rate_max[VDD_LOWER] =

		337500000;

		337500;

	disp_cc_mdss_edp_pixel_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] =

		371500000;

		371500;

	disp_cc_mdss_edp_pixel_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] =

		675000000;

		675000;

}



static int disp_cc_sm8150_fixup(struct platform_device *pdev,