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Commit 2eafeb6a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf events changes from Ingo Molnar:

 "- kernel side:

   - Intel uncore PMU support for Nehalem and Sandy Bridge CPUs, we
     support both the events available via the MSR and via the PCI
     access space.

   - various uprobes cleanups and restructurings

   - PMU driver quirks by microcode version and required x86 microcode
     loader cleanups/robustization

   - various tracing robustness updates

   - static keys: remove obsolete static_branch()

  - tooling side:

   - GTK browser improvements

   - perf report browser: support screenshots to file

   - more automated tests

   - perf kvm improvements

   - perf bench refinements

   - build environment improvements

   - pipe mode improvements

   - libtraceevent updates, we have now hopefully merged most bits with
     the out of tree forked code base

  ... and many other goodies."

* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (138 commits)
  tracing: Check for allocation failure in __tracing_open()
  perf/x86: Fix intel_perfmon_event_mapformatting
  jump label: Remove static_branch()
  tracepoint: Use static_key_false(), since static_branch() is deprecated
  perf/x86: Uncore filter support for SandyBridge-EP
  perf/x86: Detect number of instances of uncore CBox
  perf/x86: Fix event constraint for SandyBridge-EP C-Box
  perf/x86: Use 0xff as pseudo code for fixed uncore event
  perf/x86: Save a few bytes in 'struct x86_pmu'
  perf/x86: Add a microcode revision check for SNB-PEBS
  perf/x86: Improve debug output in check_hw_exists()
  perf/x86/amd: Unify AMD's generic and family 15h pmus
  perf/x86: Move Intel specific code to intel_pmu_init()
  perf/x86: Rename Intel specific macros
  perf/x86: Fix USER/KERNEL tagging of samples
  perf tools: Split event symbols arrays to hw and sw parts
  perf tools: Split out PE_VALUE_SYM parsing token to SW and HW tokens
  perf tools: Add empty rule for new line in event syntax parsing
  perf test: Use ARRAY_SIZE in parse events tests
  tools lib traceevent: Cleanup realloc use
  ...
parents 16d286e6 6e0f17be

arch/x86/include/asm/kvm_host.h

+2 −2
Original line number Diff line number Diff line
@@ -313,8 +313,8 @@ struct kvm_pmu { 
	u64 counter_bitmask[2];

	u64 global_ctrl_mask;

	u8 version;

	struct kvm_pmc gp_counters[X86_PMC_MAX_GENERIC];

	struct kvm_pmc fixed_counters[X86_PMC_MAX_FIXED];

	struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];

	struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];

	struct irq_work irq_work;

	u64 reprogram_pmi;

};

arch/x86/include/asm/msr.h

+5 −41
Original line number Diff line number Diff line
@@ -115,8 +115,8 @@ notrace static inline int native_write_msr_safe(unsigned int msr, 


extern unsigned long long native_read_tsc(void);



extern int native_rdmsr_safe_regs(u32 regs[8]);

extern int native_wrmsr_safe_regs(u32 regs[8]);

extern int rdmsr_safe_regs(u32 regs[8]);

extern int wrmsr_safe_regs(u32 regs[8]);



static __always_inline unsigned long long __native_read_tsc(void)

{
@@ -187,43 +187,6 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) 
	return err;

}



static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)

{

	u32 gprs[8] = { 0 };

	int err;



	gprs[1] = msr;

	gprs[7] = 0x9c5a203a;



	err = native_rdmsr_safe_regs(gprs);



	*p = gprs[0] | ((u64)gprs[2] << 32);



	return err;

}



static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)

{

	u32 gprs[8] = { 0 };



	gprs[0] = (u32)val;

	gprs[1] = msr;

	gprs[2] = val >> 32;

	gprs[7] = 0x9c5a203a;



	return native_wrmsr_safe_regs(gprs);

}



static inline int rdmsr_safe_regs(u32 regs[8])

{

	return native_rdmsr_safe_regs(regs);

}



static inline int wrmsr_safe_regs(u32 regs[8])

{

	return native_wrmsr_safe_regs(regs);

}



#define rdtscl(low)						\

	((low) = (u32)__native_read_tsc())
@@ -237,6 +200,8 @@ do { \ 
	(high) = (u32)(_l >> 32);			\

} while (0)



#define rdpmcl(counter, val) ((val) = native_read_pmc(counter))



#define rdtscp(low, high, aux)					\

do {                                                            \

	unsigned long long _val = native_read_tscp(&(aux));     \
@@ -248,8 +213,7 @@ do { \ 


#endif	/* !CONFIG_PARAVIRT */





#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),		\

#define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val),		\

					     (u32)((val) >> 32))



#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))

arch/x86/include/asm/paravirt.h

+2 −39
Original line number Diff line number Diff line
@@ -128,21 +128,11 @@ static inline u64 paravirt_read_msr(unsigned msr, int *err) 
	return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);

}



static inline int paravirt_rdmsr_regs(u32 *regs)

{

	return PVOP_CALL1(int, pv_cpu_ops.rdmsr_regs, regs);

}



static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)

{

	return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);

}



static inline int paravirt_wrmsr_regs(u32 *regs)

{

	return PVOP_CALL1(int, pv_cpu_ops.wrmsr_regs, regs);

}



/* These should all do BUG_ON(_err), but our headers are too tangled. */

#define rdmsr(msr, val1, val2)			\

do {						\
@@ -176,9 +166,6 @@ do { \ 
	_err;					\

})



#define rdmsr_safe_regs(regs)	paravirt_rdmsr_regs(regs)

#define wrmsr_safe_regs(regs)	paravirt_wrmsr_regs(regs)



static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)

{

	int err;
@@ -186,32 +173,6 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) 
	*p = paravirt_read_msr(msr, &err);

	return err;

}

static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)

{

	u32 gprs[8] = { 0 };

	int err;



	gprs[1] = msr;

	gprs[7] = 0x9c5a203a;



	err = paravirt_rdmsr_regs(gprs);



	*p = gprs[0] | ((u64)gprs[2] << 32);



	return err;

}



static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)

{

	u32 gprs[8] = { 0 };



	gprs[0] = (u32)val;

	gprs[1] = msr;

	gprs[2] = val >> 32;

	gprs[7] = 0x9c5a203a;



	return paravirt_wrmsr_regs(gprs);

}



static inline u64 paravirt_read_tsc(void)

{
@@ -252,6 +213,8 @@ do { \ 
	high = _l >> 32;			\

} while (0)



#define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))



static inline unsigned long long paravirt_rdtscp(unsigned int *aux)

{

	return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);

arch/x86/include/asm/paravirt_types.h

+0 −2
Original line number Diff line number Diff line
@@ -153,9 +153,7 @@ struct pv_cpu_ops { 
	/* MSR, PMC and TSR operations.

	   err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */

	u64 (*read_msr)(unsigned int msr, int *err);

	int (*rdmsr_regs)(u32 *regs);

	int (*write_msr)(unsigned int msr, unsigned low, unsigned high);

	int (*wrmsr_regs)(u32 *regs);



	u64 (*read_tsc)(void);

	u64 (*read_pmc)(int counter);

arch/x86/include/asm/perf_event.h

+11 −11
Original line number Diff line number Diff line
@@ -5,11 +5,10 @@ 
 * Performance event hw details:

 */



#define X86_PMC_MAX_GENERIC				       32

#define X86_PMC_MAX_FIXED					3

#define INTEL_PMC_MAX_GENERIC				       32

#define INTEL_PMC_MAX_FIXED					3

#define INTEL_PMC_IDX_FIXED				       32



#define X86_PMC_IDX_GENERIC				        0

#define X86_PMC_IDX_FIXED				       32

#define X86_PMC_IDX_MAX					       64



#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
@@ -48,8 +47,7 @@ 
	(X86_RAW_EVENT_MASK          |  \

	 AMD64_EVENTSEL_EVENT)

#define AMD64_NUM_COUNTERS				4

#define AMD64_NUM_COUNTERS_F15H				6

#define AMD64_NUM_COUNTERS_MAX				AMD64_NUM_COUNTERS_F15H

#define AMD64_NUM_COUNTERS_CORE				6



#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
@@ -121,16 +119,16 @@ struct x86_pmu_capability { 


/* Instr_Retired.Any: */

#define MSR_ARCH_PERFMON_FIXED_CTR0	0x309

#define X86_PMC_IDX_FIXED_INSTRUCTIONS	(X86_PMC_IDX_FIXED + 0)

#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS	(INTEL_PMC_IDX_FIXED + 0)



/* CPU_CLK_Unhalted.Core: */

#define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a

#define X86_PMC_IDX_FIXED_CPU_CYCLES	(X86_PMC_IDX_FIXED + 1)

#define INTEL_PMC_IDX_FIXED_CPU_CYCLES	(INTEL_PMC_IDX_FIXED + 1)



/* CPU_CLK_Unhalted.Ref: */

#define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b

#define X86_PMC_IDX_FIXED_REF_CYCLES	(X86_PMC_IDX_FIXED + 2)

#define X86_PMC_MSK_FIXED_REF_CYCLES	(1ULL << X86_PMC_IDX_FIXED_REF_CYCLES)

#define INTEL_PMC_IDX_FIXED_REF_CYCLES	(INTEL_PMC_IDX_FIXED + 2)

#define INTEL_PMC_MSK_FIXED_REF_CYCLES	(1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)



/*

 * We model BTS tracing as another fixed-mode PMC.
@@ -139,7 +137,7 @@ struct x86_pmu_capability { 
 * values are used by actual fixed events and higher values are used

 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.

 */

#define X86_PMC_IDX_FIXED_BTS				(X86_PMC_IDX_FIXED + 16)

#define INTEL_PMC_IDX_FIXED_BTS				(INTEL_PMC_IDX_FIXED + 16)



/*

 * IBS cpuid feature detection
@@ -234,6 +232,7 @@ struct perf_guest_switch_msr { 


extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);

extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);

extern void perf_check_microcode(void);

#else

static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr)

{
@@ -247,6 +246,7 @@ static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) 
}



static inline void perf_events_lapic_init(void)	{ }

static inline void perf_check_microcode(void) { }

#endif



#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)