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Commit 2d0fc2f1 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Modify UART pins configurations SM8150"

parents 9978f220 3bf81ec8

arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi

+22 −13
Original line number Diff line number Diff line
@@ -246,39 +246,48 @@ 
				config {

					pins = "gpio85", "gpio86";

					drive-strength = <2>;

					bias-disable;

					bias-pull-down;

				};

			};

		};



		qupv3_se13_4uart_pins: qupv3_se13_4uart_pins {

			qupv3_se13_4uart_active: qupv3_se13_4uart_active {

			qupv3_se13_ctsrx: qupv3_se13_ctsrx {

				mux {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					pins = "gpio43", "gpio46";

					function = "qup13";

				};



				config {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					pins = "gpio43", "gpio46";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se13_4uart_sleep: qupv3_se13_4uart_sleep {

			qupv3_se13_rts: qupv3_se13_rts {

				mux {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					function = "gpio";

					pins = "gpio44";

					function = "qup13";

				};



				config {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					pins = "gpio44";

					drive-strength = <2>;

					bias-disable;

					bias-pull-down;

				};

			};



			qupv3_se13_tx: qupv3_se13_tx {

				mux {

					pins = "gpio45";

					function = "qup13";

				};



				config {

					pins = "gpio45";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};

arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -421,8 +421,10 @@ 
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se13_4uart_active>;

		pinctrl-1 = <&qupv3_se13_4uart_sleep>;

		pinctrl-0 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,

						<&qupv3_se13_tx>;

		pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,

						<&qupv3_se13_tx>;

		interrupts-extended = <&pdc GIC_SPI 585 0>,

				<&tlmm 46 0>;

		qcom,wrapper-core = <&qupv3_2>;