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Commit 2ceedf97 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-4.13-rc1' of git://git.infradead.org/users/vkoul/slave-dma 

Pull dmaengine updates from Vinod Koul:

 - removal of AVR32 support in dw driver as AVR32 is gone

 - new driver for Broadcom stream buffer accelerator (SBA) RAID driver

 - add support for Faraday Technology FTDMAC020 in amba-pl08x driver

 - IOMMU support in pl330 driver

 - updates to bunch of drivers

* tag 'dmaengine-4.13-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (36 commits)
  dmaengine: qcom_hidma: correct API violation for submit
  dmaengine: zynqmp_dma: Remove max len check in zynqmp_dma_prep_memcpy
  dmaengine: tegra-apb: Really fix runtime-pm usage
  dmaengine: fsl_raid: make of_device_ids const.
  dmaengine: qcom_hidma: allow ACPI/DT parameters to be overridden
  dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly
  dmaengine: Kconfig: Simplify the help text for MXS_DMA
  dmaengine: pl330: Delete unused functions
  dmaengine: Replace WARN_TAINT_ONCE() with pr_warn_once()
  dmaengine: Kconfig: Extend the dependency for MXS_DMA
  dmaengine: mxs: Use %zu for printing a size_t variable
  dmaengine: ste_dma40: Cleanup scatterlist layering violations
  dmaengine: imx-dma: cleanup scatterlist layering violations
  dmaengine: use proper name for the R-Car SoC
  dmaengine: imx-sdma: Fix compilation warning.
  dmaengine: imx-sdma: Handle return value of clk_prepare_enable
  dmaengine: pl330: Add IOMMU support to slave tranfers
  dmaengine: DW DMAC: Handle return value of clk_prepare_enable
  dmaengine: pl08x: use GENMASK() to create bitmasks
  dmaengine: pl08x: Add support for Faraday Technology FTDMAC020
  ...
parents 09b56d5a 3edc8502

Documentation/devicetree/bindings/dma/arm-pl08x.txt

+7 −2
Original line number Original line Diff line number Diff line
@@ -3,6 +3,11 @@ 
Required properties:

Required properties:

- compatible: "arm,pl080", "arm,primecell";

- compatible: "arm,pl080", "arm,primecell";

	      "arm,pl081", "arm,primecell";

	      "arm,pl081", "arm,primecell";

	      "faraday,ftdmac020", "arm,primecell"

- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded

  in the hardware and must be specified here as <0x0003b080>. This number

  follows the PrimeCell standard numbering using the JEP106 vendor code 0x38

  for Faraday Technology.

- reg: Address range of the PL08x registers

- reg: Address range of the PL08x registers

- interrupt: The PL08x interrupt number

- interrupt: The PL08x interrupt number

- clocks: The clock running the IP core clock

- clocks: The clock running the IP core clock
@@ -20,8 +25,8 @@ Optional properties: 
- dma-requests: contains the total number of DMA requests supported by the DMAC

- dma-requests: contains the total number of DMA requests supported by the DMAC

- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32

- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32

  64, 128 or 256 bytes are legal values

  64, 128 or 256 bytes are legal values

- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal

- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal

  values

  values, the Faraday FTDMAC020 can also accept 64 bits





Clients

Clients

Required properties:

Required properties:

Documentation/devicetree/bindings/dma/brcm,iproc-sba.txt

0 → 100644
+29 −0
Original line number Original line Diff line number Diff line 
* Broadcom SBA RAID engine



Required properties:

- compatible: Should be one of the following

	      "brcm,iproc-sba"

	      "brcm,iproc-sba-v2"

  The "brcm,iproc-sba" has support for only 6 PQ coefficients

  The "brcm,iproc-sba-v2" has support for only 30 PQ coefficients

- mboxes: List of phandle and mailbox channel specifiers



Example:



raid_mbox: mbox@67400000 {

	...

	#mbox-cells = <3>;

	...

};



raid0 {

	compatible = "brcm,iproc-sba-v2";

	mboxes = <&raid_mbox 0 0x1 0xffff>,

		 <&raid_mbox 1 0x1 0xffff>,

		 <&raid_mbox 2 0x1 0xffff>,

		 <&raid_mbox 3 0x1 0xffff>,

		 <&raid_mbox 4 0x1 0xffff>,

		 <&raid_mbox 5 0x1 0xffff>,

		 <&raid_mbox 6 0x1 0xffff>,

		 <&raid_mbox 7 0x1 0xffff>;

};

Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

+3 −2
Original line number Original line Diff line number Diff line
@@ -30,8 +30,9 @@ Required Properties: 




- interrupts: interrupt specifiers for the DMAC, one for each entry in

- interrupts: interrupt specifiers for the DMAC, one for each entry in

  interrupt-names.

  interrupt-names.

- interrupt-names: one entry per channel, named "ch%u", where %u is the

- interrupt-names: one entry for the error interrupt, named "error", plus one

  channel number ranging from zero to the number of channels minus one.

  entry per channel, named "ch%u", where %u is the channel number ranging from

  zero to the number of channels minus one.





- clock-names: "fck" for the functional clock

- clock-names: "fck" for the functional clock

- clocks: a list of phandle + clock-specifier pairs, one for each entry

- clocks: a list of phandle + clock-specifier pairs, one for each entry

Documentation/devicetree/bindings/dma/shdma.txt

+1 −1
Original line number Original line Diff line number Diff line 
* SHDMA Device Tree bindings

* SHDMA Device Tree bindings





Sh-/r-mobile and r-car systems often have multiple identical DMA controller

Sh-/r-mobile and R-Car systems often have multiple identical DMA controller

instances, capable of serving any of a common set of DMA slave devices, using

instances, capable of serving any of a common set of DMA slave devices, using

the same configuration. To describe this topology we require all compatible

the same configuration. To describe this topology we require all compatible

SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible

SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible

arch/arm/mach-lpc32xx/phy3250.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -137,6 +137,9 @@ static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) 
}

}





static struct pl08x_platform_data pl08x_pd = {

static struct pl08x_platform_data pl08x_pd = {

	/* Some reasonable memcpy defaults */

	.memcpy_burst_size = PL08X_BURST_SZ_256,

	.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,

	.slave_channels = &pl08x_slave_channels[0],

	.slave_channels = &pl08x_slave_channels[0],

	.num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),

	.num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),

	.get_xfer_signal = pl08x_get_signal,

	.get_xfer_signal = pl08x_get_signal,