UPSTREAM commit 'f52774d8' 10/16

* commit 'f52774d8':
  msm: camera: flash: Remove race condition in subdev close
  msm: camera: csiphy: Initialize 2phase clock mask
  msm: camera: reject request id earlier than last flush request
  msm: camera: isp: start CSID with clock rate per sensor
  msm: camera: core: Change log message to rate limited
  msm: camera: fd: Fix the order of clearing and handling IRQs
  msm: camera: isp: Delay the change in BW during stop
  msm: camera: icp: Use icp base while disabling A5
  msm: camera: Return error in case of secure scm call failure
  msm: camera: csid: Disable CSI Rx if non-fatal errors exceed threshold
  ARM: dts: msm: Update lowsvs and turbo clks for IFE on sm8150 target
  msm: camera: isp: Add check for rdi only usecases
  msm: camera: Block release if device is active on link
  msm: camera: core: Change log type in deinit sync object
  ARM: dts: msm: Add Camnoc register map to VFE for sm8150
  msm: camera: isp: Dump last active request on HW error
  msm: camera: lrme: program the correct value to stride register
  ARM: dts: msm: Add register base address for sdm6150
  msm: camera: sync: Allow drivers to register cb for the same fence id
  msm: camera: lrme: set the HW state regardless of stop result
  ARM: dts: msm: Add camera actuator regulator load-current

Change-Id: I87f025187685901a7098581b24ad7aff892f5ada
Signed-off-by: Venkat Chinta <vchinta@codeaurora.org>
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>