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Commit 2c8aaf71 authored by Jonas Gorski's avatar Jonas Gorski Committed by Ralf Baechle
Browse files

MIPS: BCM63XX: add basic BCM6362 support 



Add basic support for detecting and booting the BCM6362.

Signed-off-by: default avatarJonas Gorski <jogo@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5009/


Acked-by: default avatarJohn Crispin <blogic@openwrt.org>
parent 13be798c

arch/mips/bcm63xx/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -25,6 +25,10 @@ config BCM63XX_CPU_6358 
	bool "support 6358 CPU"

	select HW_HAS_PCI



config BCM63XX_CPU_6362

	bool "support 6362 CPU"

	select HW_HAS_PCI



config BCM63XX_CPU_6368

	bool "support 6368 CPU"

	select HW_HAS_PCI

arch/mips/bcm63xx/boards/board_bcm963xx.c

+3 −3
Original line number Diff line number Diff line
@@ -726,11 +726,11 @@ void __init board_prom_init(void) 
	u32 val;



	/* read base address of boot chip select (0)

	 * 6328 does not have MPI but boots from a fixed address

	 * 6328/6362 do not have MPI but boot from a fixed address

	 */

	if (BCMCPU_IS_6328())

	if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {

		val = 0x18000000;

	else {

	} else {

		val = bcm_mpi_readl(MPI_CSBASE_REG(0));

		val &= MPI_CSBASE_BASE_MASK;

	}

arch/mips/bcm63xx/cpu.c

+50 −1
Original line number Diff line number Diff line
@@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = { 


};



static const unsigned long bcm6362_regs_base[] = {

	__GEN_CPU_REGS_TABLE(6362)

};



static const int bcm6362_irqs[] = {

	__GEN_CPU_IRQ_TABLE(6362)



};



static const unsigned long bcm6368_regs_base[] = {

	__GEN_CPU_REGS_TABLE(6368)

};
@@ -169,6 +178,42 @@ static unsigned int detect_cpu_clock(void) 
		return (16 * 1000000 * n1 * n2) / m1;

	}



	case BCM6362_CPU_ID:

	{

		unsigned int tmp, mips_pll_fcvo;



		tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);

		mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)

				>> STRAPBUS_6362_FCVO_SHIFT;

		switch (mips_pll_fcvo) {

		case 0x03:

		case 0x0b:

		case 0x13:

		case 0x1b:

			return 240000000;

		case 0x04:

		case 0x0c:

		case 0x14:

		case 0x1c:

			return 160000000;

		case 0x05:

		case 0x0e:

		case 0x16:

		case 0x1e:

		case 0x1f:

			return 400000000;

		case 0x06:

			return 440000000;

		case 0x07:

		case 0x17:

			return 384000000;

		case 0x15:

		case 0x1d:

			return 200000000;

		default:

			return 320000000;

		}

	}

	case BCM6368_CPU_ID:

	{

		unsigned int tmp, p1, p2, ndiv, m1;
@@ -205,7 +250,7 @@ static unsigned int detect_memory_size(void) 
	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;

	u32 val;



	if (BCMCPU_IS_6328())

	if (BCMCPU_IS_6328() || BCMCPU_IS_6362())

		return bcm_ddr_readl(DDR_CSEND_REG) << 24;



	if (BCMCPU_IS_6345()) {
@@ -297,6 +342,10 @@ void __init bcm63xx_cpu_init(void) 
		bcm63xx_regs_base = bcm6358_regs_base;

		bcm63xx_irqs = bcm6358_irqs;

		break;

	case BCM6362_CPU_ID:

		bcm63xx_regs_base = bcm6362_regs_base;

		bcm63xx_irqs = bcm6362_irqs;

		break;

	case BCM6368_CPU_ID:

		bcm63xx_regs_base = bcm6368_regs_base;

		bcm63xx_irqs = bcm6368_irqs;

arch/mips/bcm63xx/irq.c

+22 −0
Original line number Diff line number Diff line
@@ -82,6 +82,17 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; 
#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6358

#define ext_irq_cfg_reg2	0

#endif

#ifdef CONFIG_BCM63XX_CPU_6362

#define irq_stat_reg		PERF_IRQSTAT_6362_REG

#define irq_mask_reg		PERF_IRQMASK_6362_REG

#define irq_bits		64

#define is_ext_irq_cascaded	1

#define ext_irq_start		(BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)

#define ext_irq_end		(BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)

#define ext_irq_count		4

#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6362

#define ext_irq_cfg_reg2	0

#endif

#ifdef CONFIG_BCM63XX_CPU_6368

#define irq_stat_reg		PERF_IRQSTAT_6368_REG

#define irq_mask_reg		PERF_IRQMASK_6368_REG
@@ -170,6 +181,16 @@ static void bcm63xx_init_irq(void) 
		ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;

		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;

		break;

	case BCM6362_CPU_ID:

		irq_stat_addr += PERF_IRQSTAT_6362_REG;

		irq_mask_addr += PERF_IRQMASK_6362_REG;

		irq_bits = 64;

		ext_irq_count = 4;

		is_ext_irq_cascaded = 1;

		ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;

		ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;

		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;

		break;

	case BCM6368_CPU_ID:

		irq_stat_addr += PERF_IRQSTAT_6368_REG;

		irq_mask_addr += PERF_IRQMASK_6368_REG;
@@ -458,6 +479,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, 
	case BCM6338_CPU_ID:

	case BCM6345_CPU_ID:

	case BCM6358_CPU_ID:

	case BCM6362_CPU_ID:

	case BCM6368_CPU_ID:

		if (levelsense)

			reg |= EXTIRQ_CFG_LEVELSENSE(irq);

arch/mips/bcm63xx/prom.c

+2 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ void __init prom_init(void) 
		mask = CKCTL_6348_ALL_SAFE_EN;

	else if (BCMCPU_IS_6358())

		mask = CKCTL_6358_ALL_SAFE_EN;

	else if (BCMCPU_IS_6362())

		mask = CKCTL_6362_ALL_SAFE_EN;

	else if (BCMCPU_IS_6368())

		mask = CKCTL_6368_ALL_SAFE_EN;

	else