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Commit 2b48be65 authored by Chaitra P B's avatar Chaitra P B Committed by Martin K. Petersen
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scsi: mpt3sas: As per MPI-spec, use combined reply queue for SAS3.5... 


scsi: mpt3sas: As per MPI-spec, use combined reply queue for SAS3.5 controllers when HBA supports more than 16 MSI-x vectors.

Presently driver is using combined reply queue feature when MSI-x vectors >
8 for both SAS3 and SAS3.5 controllers.  But as per MPI-spec,

1. For SAS3 controllers, driver should use combined reply queue when HBA
supports more than 8 MSI-x vectors.

2. For SAS3.5 controllers, driver should use combined reply queue when HBA
supports more than 16 MSI-x vectors.

Modified driver code to use combined reply queue for SAS3 controllers when
HBA supports > 8 MSI-x vectors and for SAS3.5 controllers when HBA supports
> 16 MSI-x vectors.

Signed-off-by: default avatarChaitra P B <chaitra.basappa@broadcom.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent d37306ca

drivers/scsi/mpt3sas/mpt3sas_base.c

+8 −7
Original line number Diff line number Diff line
@@ -2952,10 +2952,9 @@ mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) 
	_base_free_irq(ioc);

	_base_disable_msix(ioc);



	if (ioc->combined_reply_queue) {

	kfree(ioc->replyPostRegisterIndex);

	ioc->replyPostRegisterIndex = NULL;

	}





	if (ioc->chip_phys) {

		iounmap(ioc->chip);
@@ -3062,7 +3061,7 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) 
	/* Use the Combined reply queue feature only for SAS3 C0 & higher

	 * revision HBAs and also only when reply queue count is greater than 8

	 */

	if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) {

	if (ioc->combined_reply_queue) {

		/* Determine the Supplemental Reply Post Host Index Registers

		 * Addresse. Supplemental Reply Post Host Index Registers

		 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
@@ -3086,8 +3085,7 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) 
			     MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +

			     (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));

		}

	} else

		ioc->combined_reply_queue = 0;

	}



	if (ioc->is_warpdrive) {

		ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
@@ -5705,6 +5703,9 @@ _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) 
	facts->WhoInit = mpi_reply.WhoInit;

	facts->NumberOfPorts = mpi_reply.NumberOfPorts;

	facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;

	if (ioc->msix_enable && (facts->MaxMSIxVectors <=

	    MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc)))

		ioc->combined_reply_queue = 0;

	facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);

	facts->MaxReplyDescriptorPostQueueDepth =

	    le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);

drivers/scsi/mpt3sas/mpt3sas_base.h

+1 −0
Original line number Diff line number Diff line
@@ -323,6 +323,7 @@ 
 * There are twelve Supplemental Reply Post Host Index Registers

 * and each register is at offset 0x10 bytes from the previous one.

 */

#define MAX_COMBINED_MSIX_VECTORS(gen35) ((gen35 == 1) ? 16 : 8)

#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G3	12

#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G35	16

#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET	(0x10)