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Commit 2990a1fc authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: rename ip block helper functions 



add device to the name for consistency.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f5ec697e

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+20 −18
Original line number Diff line number Diff line
@@ -224,16 +224,17 @@ enum amdgpu_kiq_irq { 
	AMDGPU_CP_KIQ_IRQ_LAST

};



int amdgpu_set_clockgating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,

					   enum amd_ip_block_type block_type,

					   enum amd_clockgating_state state);

int amdgpu_set_powergating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,

					   enum amd_ip_block_type block_type,

					   enum amd_powergating_state state);

void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);

int amdgpu_wait_for_idle(struct amdgpu_device *adev,

void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,

					    u32 *flags);

int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,

				   enum amd_ip_block_type block_type);

bool amdgpu_is_idle(struct amdgpu_device *adev,

bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,

			      enum amd_ip_block_type block_type);



#define AMDGPU_MAX_IP_NUM 16
@@ -259,14 +260,15 @@ struct amdgpu_ip_block { 
	const struct amdgpu_ip_block_version *version;

};



int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,

int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,

				       enum amd_ip_block_type type,

				       u32 major, u32 minor);



struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,

struct amdgpu_ip_block *

amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,

			      enum amd_ip_block_type type);



int amdgpu_ip_block_add(struct amdgpu_device *adev,

int amdgpu_device_ip_block_add(struct amdgpu_device *adev,

			       const struct amdgpu_ip_block_version *ip_block_version);



/* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c

+1 −1
Original line number Diff line number Diff line
@@ -277,7 +277,7 @@ static int acp_hw_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	const struct amdgpu_ip_block *ip_block =

		amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);

		amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);



	if (!ip_block)

		return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+26 −24
Original line number Diff line number Diff line
@@ -937,7 +937,7 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { 
	.can_switch = amdgpu_switcheroo_can_switch,

};



int amdgpu_set_clockgating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,

					   enum amd_ip_block_type block_type,

					   enum amd_clockgating_state state)

{
@@ -959,7 +959,7 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 
	return r;

}



int amdgpu_set_powergating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,

					   enum amd_ip_block_type block_type,

					   enum amd_powergating_state state)

{
@@ -981,7 +981,8 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev, 
	return r;

}



void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)

void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,

					    u32 *flags)

{

	int i;
@@ -993,7 +994,7 @@ void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) 
	}

}



int amdgpu_wait_for_idle(struct amdgpu_device *adev,

int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,

				   enum amd_ip_block_type block_type)

{

	int i, r;
@@ -1012,7 +1013,7 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev, 


}



bool amdgpu_is_idle(struct amdgpu_device *adev,

bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,

			      enum amd_ip_block_type block_type)

{

	int i;
@@ -1027,7 +1028,8 @@ bool amdgpu_is_idle(struct amdgpu_device *adev, 


}



struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,

struct amdgpu_ip_block *

amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,

			      enum amd_ip_block_type type)

{

	int i;
@@ -1040,7 +1042,7 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 
}



/**

 * amdgpu_ip_block_version_cmp

 * amdgpu_device_ip_block_version_cmp

 *

 * @adev: amdgpu_device pointer

 * @type: enum amd_ip_block_type
@@ -1050,11 +1052,11 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 
 * return 0 if equal or greater

 * return 1 if smaller or the ip_block doesn't exist

 */

int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,

int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,

				       enum amd_ip_block_type type,

				       u32 major, u32 minor)

{

	struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);

	struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);



	if (ip_block && ((ip_block->version->major > major) ||

			((ip_block->version->major == major) &&
@@ -1065,7 +1067,7 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 
}



/**

 * amdgpu_ip_block_add

 * amdgpu_device_ip_block_add

 *

 * @adev: amdgpu_device pointer

 * @ip_block_version: pointer to the IP to add
@@ -1073,7 +1075,7 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 
 * Adds the IP block driver information to the collection of IPs

 * on the asic.

 */

int amdgpu_ip_block_add(struct amdgpu_device *adev,

int amdgpu_device_ip_block_add(struct amdgpu_device *adev,

			       const struct amdgpu_ip_block_version *ip_block_version)

{

	if (!ip_block_version)
@@ -1569,7 +1571,7 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev) 
		amdgpu_virt_request_full_gpu(adev, false);



	/* ungate SMC block first */

	r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,

	r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,

						   AMD_CG_STATE_UNGATE);

	if (r) {

		DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+9 −9
Original line number Diff line number Diff line
@@ -1278,15 +1278,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 
			/* XXX select vce level based on ring/task */

			adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;

			mutex_unlock(&adev->pm.mutex);

			amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,

			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,

							       AMD_CG_STATE_UNGATE);

			amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,

			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,

							       AMD_PG_STATE_UNGATE);

			amdgpu_pm_compute_clocks(adev);

		} else {

			amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,

			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,

							       AMD_PG_STATE_GATE);

			amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,

			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,

							       AMD_CG_STATE_GATE);

			mutex_lock(&adev->pm.mutex);

			adev->pm.dpm.vce_active = false;
@@ -1584,7 +1584,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) 
	struct drm_device *ddev = adev->ddev;

	u32 flags = 0;



	amdgpu_get_clockgating_state(adev, &flags);

	amdgpu_device_ip_get_clockgating_state(adev, &flags);

	seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);

	amdgpu_parse_cg_state(m, flags);

	seq_printf(m, "\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

+9 −9
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 
	}



	/* from uvd v5.0 HW addressing capacity increased to 64 bits */

	if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))

	if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))

		adev->uvd.address_64_bit = true;



	switch (adev->asic_type) {
@@ -1153,9 +1153,9 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 
		} else {

			amdgpu_asic_set_uvd_clocks(adev, 0, 0);

			/* shutdown the UVD block */

			amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

							       AMD_PG_STATE_GATE);

			amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

							       AMD_CG_STATE_GATE);

		}

	} else {
@@ -1176,9 +1176,9 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 
			amdgpu_dpm_enable_uvd(adev, true);

		} else {

			amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);

			amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

							       AMD_CG_STATE_UNGATE);

			amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

							       AMD_PG_STATE_UNGATE);

		}

	}