Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 28c1c9fa authored by KarimAllah Ahmed's avatar KarimAllah Ahmed Committed by Thomas Gleixner
Browse files

KVM/VMX: Emulate MSR_IA32_ARCH_CAPABILITIES 



Intel processors use MSR_IA32_ARCH_CAPABILITIES MSR to indicate RDCL_NO
(bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default the
contents will come directly from the hardware, but user-space can still
override it.

[dwmw2: The bit in kvm_cpuid_7_0_edx_x86_features can be unconditional]

Signed-off-by: default avatarKarimAllah Ahmed <karahmed@amazon.de>
Signed-off-by: default avatarDavid Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Reviewed-by: default avatarDarren Kenny <darren.kenny@oracle.com>
Reviewed-by: default avatarJim Mattson <jmattson@google.com>
Reviewed-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jun Nakajima <jun.nakajima@intel.com>
Cc: kvm@vger.kernel.org
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Asit Mallick <asit.k.mallick@intel.com>
Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com>
Cc: Greg KH <gregkh@linuxfoundation.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Tim Chen <tim.c.chen@linux.intel.com>
Cc: Ashok Raj <ashok.raj@intel.com>
Link: https://lkml.kernel.org/r/1517522386-18410-4-git-send-email-karahmed@amazon.de
parent 15d45071

arch/x86/kvm/cpuid.c

+1 −1
Original line number Diff line number Diff line
@@ -394,7 +394,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, 


	/* cpuid 7.0.edx*/

	const u32 kvm_cpuid_7_0_edx_x86_features =

		F(AVX512_4VNNIW) | F(AVX512_4FMAPS);

		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(ARCH_CAPABILITIES);



	/* all calls to cpuid_count() should be made on the same cpu */

	get_cpu();

arch/x86/kvm/vmx.c

+15 −0
Original line number Diff line number Diff line
@@ -594,6 +594,8 @@ struct vcpu_vmx { 
	u64 		      msr_guest_kernel_gs_base;

#endif



	u64 		      arch_capabilities;



	u32 vm_entry_controls_shadow;

	u32 vm_exit_controls_shadow;

	u32 secondary_exec_control;
@@ -3260,6 +3262,12 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
	case MSR_IA32_TSC:

		msr_info->data = guest_read_tsc(vcpu);

		break;

	case MSR_IA32_ARCH_CAPABILITIES:

		if (!msr_info->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))

			return 1;

		msr_info->data = to_vmx(vcpu)->arch_capabilities;

		break;

	case MSR_IA32_SYSENTER_CS:

		msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);

		break;
@@ -3395,6 +3403,11 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,

					      MSR_TYPE_W);

		break;

	case MSR_IA32_ARCH_CAPABILITIES:

		if (!msr_info->host_initiated)

			return 1;

		vmx->arch_capabilities = data;

		break;

	case MSR_IA32_CR_PAT:

		if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {

			if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
@@ -5657,6 +5670,8 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx) 
		++vmx->nmsrs;

	}



	if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))

		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);



	vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);

arch/x86/kvm/x86.c

+1 −0
Original line number Diff line number Diff line
@@ -1009,6 +1009,7 @@ static u32 msrs_to_save[] = { 
#endif

	MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,

	MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,

	MSR_IA32_ARCH_CAPABILITIES

};



static unsigned num_msrs_to_save;