Merge "clk: qcom: gcc-sdm429w: Update plls for SDM429W" (25f3e59a) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/clk/qcom/gcc-sdm429w.c

+26 −35

Original line number	Diff line number	Diff line
		@@ -34,7 +34,6 @@
		#define F_SLEW(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) }

		static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
		static DEFINE_VDD_REGULATORS(vdd_sr_pll, VDD_SR_PLL_NUM, 1, vdd_sr_levels);

		enum {
		P_BI_TCXO,
		@@ -354,8 +353,8 @@ static const struct parent_map gcc_parent_map_20[] = {

		static const char * const gcc_parent_names_20[] = {
		"bi_tcxo",
		"gpll0",
		"gpll6",
		"gpll0_out_main",
		"gpll6_out_aux",
		"sleep_clk",
		"core_bi_pll_test_se",
		};
		@@ -395,6 +394,17 @@ static struct clk_alpha_pll gpll0_out_main = {
		},
		};

		static struct clk_fixed_factor gpll0_out_aux = {
		.mult = 1,
		.div = 1,
		.hw.init = &(struct clk_init_data){
		.name = "gpll0_out_aux",
		.parent_names = (const char *[]){ "gpll0_out_main" },
		.num_parents = 1,
		.ops = &clk_fixed_factor_ops,
		},
		};

		static struct clk_alpha_pll gpll0_ao_out_main = {
		.offset = 0x21000,
		.soft_vote = &soft_vote_gpll0,
		@@ -412,20 +422,6 @@ static struct clk_alpha_pll gpll0_ao_out_main = {
		},
		};

		static struct clk_alpha_pll gpll1_out_main = {
		.offset = 0x20000,
		.clkr = {
		.enable_reg = 0x45000,
		.enable_mask = BIT(1),
		.hw.init = &(struct clk_init_data){
		.name = "gpll1_out_main",
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_alpha_pll_ops,
		},
		},
		};

		/* 750MHz configuration */
		static const struct alpha_pll_config gpll3_config = {
		.l = 0x27,
		@@ -474,11 +470,15 @@ static struct clk_alpha_pll gpll4_out_main = {
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_alpha_pll_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_NOMINAL] = 1400000000},
		},
		},
		};

		static struct clk_pll gpll6 = {
		static struct clk_pll gpll6_out_main = {
		.l_reg = 0x37004,
		.m_reg = 0x37008,
		.n_reg = 0x3700C,
		@@ -491,21 +491,15 @@ static struct clk_pll gpll6 = {
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_pll_ops,
		.vdd_class = &vdd_sr_pll,
		.rate_max = (unsigned long [VDD_SR_PLL_NUM]) {
		[VDD_SR_PLL_SVS] = 1080000000,
		},
		.num_rate_max = VDD_SR_PLL_NUM,
		},
		};


		static struct clk_regmap gpll6_out_aux = {
		.enable_reg = 0x45000,
		.enable_mask = BIT(7),
		.hw.init = &(struct clk_init_data){
		.name = "gpll6_out_aux",
		.parent_names = (const char *[]){ "gpll6" },
		.parent_names = (const char *[]){ "gpll6_out_main" },
		.num_parents = 1,
		.ops = &clk_pll_vote_ops,
		},
		@@ -3773,6 +3767,10 @@ static struct clk_dummy wcnss_m_clk = {
		},
		};

		struct clk_hw *gcc_sdm429w_hws[] = {
		[GPLL0_OUT_AUX] = &gpll0_out_aux.hw,
		};

		static struct clk_regmap *gcc_sdm429w_clocks[] = {
		[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
		[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
		@@ -3845,10 +3843,9 @@ static struct clk_regmap *gcc_sdm429w_clocks[] = {
		[GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
		[GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
		[GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
		[GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
		[GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
		[GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
		[GPLL6] = &gpll6.clkr,
		[GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
		[GPLL6_OUT_AUX] = &gpll6_out_aux,
		[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
		[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
		@@ -3968,6 +3965,8 @@ static const struct qcom_cc_desc gcc_sdm429w_desc = {
		.config = &gcc_sdm429w_regmap_config,
		.clks = gcc_sdm429w_clocks,
		.num_clks = ARRAY_SIZE(gcc_sdm429w_clocks),
		.hwclks = gcc_sdm429w_hws,
		.num_hwclks = ARRAY_SIZE(gcc_sdm429w_hws),
		.resets = gcc_sdm429w_resets,
		.num_resets = ARRAY_SIZE(gcc_sdm429w_resets),
		};
		@@ -3998,14 +3997,6 @@ static int gcc_sdm429w_probe(struct platform_device *pdev)
		return PTR_ERR(vdd_cx.regulator[0]);
		}

		vdd_sr_pll.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_sr_pll");
		if (IS_ERR(vdd_sr_pll.regulator[0])) {
		if (!(PTR_ERR(vdd_sr_pll.regulator[0]) == -EPROBE_DEFER))
		dev_err(&pdev->dev,
		"Unable to get vdd_sr_pll regulator\n");
		return PTR_ERR(vdd_sr_pll.regulator[0]);
		}

		regmap = qcom_cc_map(pdev, &gcc_sdm429w_desc);
		if (IS_ERR(regmap))
		return PTR_ERR(regmap);

drivers/clk/qcom/vdd-level-sdm429w.h

+12 −46

Original line number	Diff line number	Diff line
		@@ -17,57 +17,23 @@
		#include <linux/regulator/rpm-smd-regulator.h>
		#include <linux/regulator/consumer.h>

		enum vdd_dig_levels {
		enum vdd_levels {
		VDD_NONE,
		VDD_MIN, /* MIN SVS */
		VDD_LOWER, /* SVS2 */
		VDD_LOW, /* SVS */
		VDD_LOW_L1, /* SVSL1 */
		VDD_NOMINAL, /* NOM */
		VDD_NOMINAL_L1, /* NOM */
		VDD_HIGH, /* TURBO */
		VDD_NUM,
		VDD_LOW,
		VDD_LOW_L1,
		VDD_NOMINAL,
		VDD_NOMINAL_L1,
		VDD_HIGH,
		VDD_NUM
		};

		static int vdd_corner[] = {
		RPM_REGULATOR_LEVEL_NONE, /* VDD_NONE */
		RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_MIN */
		RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_LOWER */
		RPM_REGULATOR_LEVEL_SVS, /* VDD_LOW */
		RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_LOW_L1 */
		RPM_REGULATOR_LEVEL_NOM, /* VDD_NOMINAL */
		RPM_REGULATOR_LEVEL_NOM_PLUS, /* VDD_NOMINAL */
		RPM_REGULATOR_LEVEL_TURBO, /* VDD_HIGH */
		};

		enum vdd_hf_pll_levels {
		VDD_HF_PLL_OFF,
		VDD_HF_PLL_SVS,
		VDD_HF_PLL_NOM,
		VDD_HF_PLL_TUR,
		VDD_HF_PLL_NUM,
		};

		static int vdd_hf_levels[] = {
		0, RPM_REGULATOR_LEVEL_NONE, /* VDD_HF_PLL_OFF */
		1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_HF_PLL_SVS */
		1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_HF_PLL_NOM */
		1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_HF_PLL_TUR */
		};

		enum vdd_sr_pll_levels {
		VDD_SR_PLL_OFF,
		VDD_SR_PLL_SVS,
		VDD_SR_PLL_NOM,
		VDD_SR_PLL_TUR,
		VDD_SR_PLL_NUM,
		};

		static int vdd_sr_levels[] = {
		0, /* VDD_SR_PLL_OFF */
		976000, /* VDD_SR_PLL_SVS */
		976000, /* VDD_SR_PLL_NOM */
		976000, /* VDD_SR_PLL_TUR */
		RPM_REGULATOR_LEVEL_SVS, /* VDD_SVS */
		RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_SVS_PLUS */
		RPM_REGULATOR_LEVEL_NOM, /* VDD_NOM */
		RPM_REGULATOR_LEVEL_NOM_PLUS, /* VDD_NOM_PLUS */
		RPM_REGULATOR_LEVEL_TURBO, /* VDD_TURBO */
		};

		#endif

include/dt-bindings/clock/qcom,gcc-sdm429w.h

+183 −182

Original line number	Diff line number	Diff line
		@@ -16,188 +16,189 @@
		#define _DT_BINDINGS_CLK_QCOM_GCC_SDM429W_H

		#define GPLL0_OUT_MAIN 0
		#define GPLL0_AO_CLK_SRC 1
		#define GPLL1_OUT_MAIN 2
		#define GPLL3_OUT_MAIN 3
		#define GPLL4_OUT_MAIN 4
		#define GPLL0_AO_OUT_MAIN 5
		#define GPLL0_SLEEP_CLK_SRC 6
		#define GPLL6 7
		#define GPLL6_OUT_AUX 8
		#define APSS_AHB_CLK_SRC 9
		#define BLSP1_QUP1_I2C_APPS_CLK_SRC 10
		#define BLSP1_QUP1_SPI_APPS_CLK_SRC 11
		#define BLSP1_QUP2_I2C_APPS_CLK_SRC 12
		#define BLSP1_QUP2_SPI_APPS_CLK_SRC 13
		#define BLSP1_QUP3_I2C_APPS_CLK_SRC 14
		#define BLSP1_QUP3_SPI_APPS_CLK_SRC 15
		#define BLSP1_QUP4_I2C_APPS_CLK_SRC 16
		#define BLSP1_QUP4_SPI_APPS_CLK_SRC 17
		#define BLSP1_UART1_APPS_CLK_SRC 18
		#define BLSP1_UART2_APPS_CLK_SRC 19
		#define BLSP2_QUP1_I2C_APPS_CLK_SRC 20
		#define BLSP2_QUP1_SPI_APPS_CLK_SRC 21
		#define BLSP2_QUP2_I2C_APPS_CLK_SRC 22
		#define BLSP2_QUP2_SPI_APPS_CLK_SRC 23
		#define BLSP2_QUP3_I2C_APPS_CLK_SRC 24
		#define BLSP2_QUP3_SPI_APPS_CLK_SRC 25
		#define BLSP2_QUP4_I2C_APPS_CLK_SRC 26
		#define BLSP2_QUP4_SPI_APPS_CLK_SRC 27
		#define BLSP2_UART1_APPS_CLK_SRC 28
		#define BLSP2_UART2_APPS_CLK_SRC 29
		#define BYTE0_CLK_SRC 30
		#define BYTE1_CLK_SRC 31
		#define CAMSS_TOP_AHB_CLK_SRC 32
		#define CCI_CLK_SRC 33
		#define CPP_CLK_SRC 34
		#define CRYPTO_CLK_SRC 35
		#define CSI0_CLK_SRC 36
		#define CSI0PHYTIMER_CLK_SRC 37
		#define CSI1_CLK_SRC 38
		#define CSI1PHYTIMER_CLK_SRC 39
		#define CSI2_CLK_SRC 40
		#define ESC0_CLK_SRC 41
		#define ESC1_CLK_SRC 42
		#define GCC_BIMC_GFX_CLK 43
		#define GCC_BIMC_GPU_CLK 44
		#define GCC_BLSP1_AHB_CLK 45
		#define GCC_BLSP1_QUP1_I2C_APPS_CLK 46
		#define GCC_BLSP1_QUP1_SPI_APPS_CLK 47
		#define GCC_BLSP1_QUP2_I2C_APPS_CLK 48
		#define GCC_BLSP1_QUP2_SPI_APPS_CLK 49
		#define GCC_BLSP1_QUP3_I2C_APPS_CLK 50
		#define GCC_BLSP1_QUP3_SPI_APPS_CLK 51
		#define GCC_BLSP1_QUP4_I2C_APPS_CLK 52
		#define GCC_BLSP1_QUP4_SPI_APPS_CLK 53
		#define GCC_BLSP1_UART1_APPS_CLK 54
		#define GCC_BLSP1_UART2_APPS_CLK 55
		#define GCC_BLSP2_QUP1_I2C_APPS_CLK 56
		#define GCC_BLSP2_QUP1_SPI_APPS_CLK 57
		#define GCC_BLSP2_QUP2_I2C_APPS_CLK 58
		#define GCC_BLSP2_QUP2_SPI_APPS_CLK 59
		#define GCC_BLSP2_QUP3_I2C_APPS_CLK 60
		#define GCC_BLSP2_QUP3_SPI_APPS_CLK 61
		#define GCC_BLSP2_QUP4_I2C_APPS_CLK 62
		#define GCC_BLSP2_QUP4_SPI_APPS_CLK 63
		#define GCC_BLSP2_UART1_APPS_CLK 64
		#define GCC_BLSP2_UART2_APPS_CLK 65
		#define GCC_BLSP2_AHB_CLK 66
		#define GCC_BOOT_ROM_AHB_CLK 67
		#define GCC_CAMSS_AHB_CLK 68
		#define GCC_CAMSS_CCI_AHB_CLK 69
		#define GCC_CAMSS_CCI_CLK 70
		#define GCC_CAMSS_CPP_AHB_CLK 71
		#define GCC_CAMSS_CPP_AXI_CLK 72
		#define GCC_CAMSS_CPP_CLK 73
		#define GCC_CAMSS_CSI0_AHB_CLK 74
		#define GCC_CAMSS_CSI0_CLK 75
		#define GCC_CAMSS_CSI0PHY_CLK 76
		#define GCC_CAMSS_CSI0PIX_CLK 77
		#define GCC_CAMSS_CSI0RDI_CLK 78
		#define GCC_CAMSS_CSI1_AHB_CLK 79
		#define GCC_CAMSS_CSI1_CLK 80
		#define GCC_CAMSS_CSI1PHY_CLK 81
		#define GCC_CAMSS_CSI1PIX_CLK 82
		#define GCC_CAMSS_CSI1RDI_CLK 83
		#define GCC_CAMSS_CSI2_AHB_CLK 84
		#define GCC_CAMSS_CSI2_CLK 85
		#define GCC_CAMSS_CSI2PHY_CLK 86
		#define GCC_CAMSS_CSI2PIX_CLK 87
		#define GCC_CAMSS_CSI2RDI_CLK 88
		#define GCC_CAMSS_CSI_VFE0_CLK 89
		#define GCC_CAMSS_GP0_CLK_SRC 90
		#define GCC_CAMSS_GP1_CLK_SRC 91
		#define GCC_CAMSS_CSI_VFE1_CLK 92
		#define GCC_CAMSS_CSI0PHYTIMER_CLK 93
		#define GCC_CAMSS_CSI1PHYTIMER_CLK 94
		#define GCC_CAMSS_GP0_CLK 95
		#define GCC_CAMSS_GP1_CLK 96
		#define GCC_CAMSS_ISPIF_AHB_CLK 97
		#define GCC_CAMSS_JPEG0_CLK 98
		#define GCC_CAMSS_JPEG_AHB_CLK 99
		#define GCC_CAMSS_JPEG_AXI_CLK 100
		#define GCC_CAMSS_MCLK0_CLK 101
		#define GCC_CAMSS_MCLK1_CLK 102
		#define GCC_CAMSS_MCLK2_CLK 103
		#define GCC_CAMSS_MICRO_AHB_CLK 104
		#define GCC_CAMSS_TOP_AHB_CLK 105
		#define GCC_CAMSS_VFE0_CLK 106
		#define GCC_CAMSS_VFE1_AHB_CLK 107
		#define GCC_CAMSS_VFE1_AXI_CLK 108
		#define GCC_CAMSS_VFE1_CLK 109
		#define GCC_CAMSS_VFE_AHB_CLK 110
		#define GCC_CAMSS_VFE_AXI_CLK 111
		#define GCC_CRYPTO_AHB_CLK 112
		#define GCC_CRYPTO_AXI_CLK 113
		#define GCC_CRYPTO_CLK 114
		#define GCC_DCC_CLK 115
		#define GCC_GP1_CLK 116
		#define GCC_GP2_CLK 117
		#define GCC_GP3_CLK 118
		#define GCC_MDSS_AHB_CLK 119
		#define GCC_MDSS_AXI_CLK 120
		#define GCC_MDSS_BYTE0_CLK 121
		#define GCC_MDSS_BYTE1_CLK 122
		#define GCC_MDSS_ESC0_CLK 123
		#define GCC_MDSS_ESC1_CLK 124
		#define GCC_MDSS_MDP_CLK 125
		#define GCC_MDSS_PCLK0_CLK 126
		#define GCC_MDSS_PCLK1_CLK 127
		#define GCC_MDSS_VSYNC_CLK 128
		#define GCC_MSS_CFG_AHB_CLK 129
		#define GCC_MSS_Q6_BIMC_AXI_CLK 130
		#define GCC_OXILI_AHB_CLK 131
		#define GCC_OXILI_AON_CLK 132
		#define GCC_OXILI_GFX3D_CLK 133
		#define GCC_OXILI_TIMER_CLK 134
		#define GCC_PDM2_CLK 135
		#define GCC_PDM_AHB_CLK 136
		#define GCC_PRNG_AHB_CLK 137
		#define GCC_SDCC1_AHB_CLK 138
		#define GCC_SDCC1_APPS_CLK 139
		#define GCC_SDCC1_ICE_CORE_CLK 140
		#define GCC_SDCC2_AHB_CLK 141
		#define GCC_SDCC2_APPS_CLK 142
		#define GCC_USB2A_PHY_SLEEP_CLK 143
		#define GCC_USB_HS_AHB_CLK 144
		#define GCC_USB_HS_PHY_CFG_AHB_CLK 145
		#define GCC_USB_HS_SYSTEM_CLK 146
		#define GCC_VENUS0_AHB_CLK 147
		#define GCC_VENUS0_AXI_CLK 148
		#define GCC_VENUS0_CORE0_VCODEC0_CLK 149
		#define GCC_VENUS0_VCODEC0_CLK 150
		#define GCC_XO_CLK_SRC 151
		#define GFX3D_CLK_SRC 152
		#define GP1_CLK_SRC 153
		#define GP2_CLK_SRC 154
		#define GP3_CLK_SRC 155
		#define JPEG0_CLK_SRC 156
		#define MCLK0_CLK_SRC 157
		#define MCLK1_CLK_SRC 158
		#define MCLK2_CLK_SRC 159
		#define MDP_CLK_SRC 160
		#define MDSS_MDP_VOTE_CLK 161
		#define MDSS_ROTATOR_VOTE_CLK 162
		#define PCLK0_CLK_SRC 163
		#define PCLK1_CLK_SRC 164
		#define PDM2_CLK_SRC 165
		#define SDCC1_APPS_CLK_SRC 166
		#define SDCC1_ICE_CORE_CLK_SRC 167
		#define SDCC2_APPS_CLK_SRC 168
		#define USB_HS_SYSTEM_CLK_SRC 169
		#define VCODEC0_CLK_SRC 170
		#define VFE0_CLK_SRC 171
		#define VFE1_CLK_SRC 172
		#define VSYNC_CLK_SRC 173
		#define GCC_APSS_TCU_CLK 174
		#define GCC_CPP_TBU_CLK 175
		#define GCC_JPEG_TBU_CLK 176
		#define GCC_MDP_TBU_CLK 177
		#define GCC_SMMU_CFG_CLK 178
		#define GCC_VENUS_TBU_CLK 179
		#define GCC_VFE_TBU_CLK 180
		#define GCC_VFE1_TBU_CLK 181
		#define GCC_QDSS_DAP_CLK 182
		#define GPLL0_OUT_AUX 1
		#define GPLL0_AO_CLK_SRC 2
		#define GPLL1_OUT_MAIN 3
		#define GPLL3_OUT_MAIN 4
		#define GPLL4_OUT_MAIN 5
		#define GPLL0_AO_OUT_MAIN 6
		#define GPLL0_SLEEP_CLK_SRC 7
		#define GPLL6_OUT_MAIN 8
		#define GPLL6_OUT_AUX 9
		#define APSS_AHB_CLK_SRC 10
		#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11
		#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12
		#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13
		#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14
		#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15
		#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16
		#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17
		#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18
		#define BLSP1_UART1_APPS_CLK_SRC 19
		#define BLSP1_UART2_APPS_CLK_SRC 20
		#define BLSP2_QUP1_I2C_APPS_CLK_SRC 21
		#define BLSP2_QUP1_SPI_APPS_CLK_SRC 22
		#define BLSP2_QUP2_I2C_APPS_CLK_SRC 23
		#define BLSP2_QUP2_SPI_APPS_CLK_SRC 24
		#define BLSP2_QUP3_I2C_APPS_CLK_SRC 25
		#define BLSP2_QUP3_SPI_APPS_CLK_SRC 26
		#define BLSP2_QUP4_I2C_APPS_CLK_SRC 27
		#define BLSP2_QUP4_SPI_APPS_CLK_SRC 28
		#define BLSP2_UART1_APPS_CLK_SRC 29
		#define BLSP2_UART2_APPS_CLK_SRC 30
		#define BYTE0_CLK_SRC 31
		#define BYTE1_CLK_SRC 32
		#define CAMSS_TOP_AHB_CLK_SRC 33
		#define CCI_CLK_SRC 34
		#define CPP_CLK_SRC 35
		#define CRYPTO_CLK_SRC 36
		#define CSI0_CLK_SRC 37
		#define CSI0PHYTIMER_CLK_SRC 38
		#define CSI1_CLK_SRC 39
		#define CSI1PHYTIMER_CLK_SRC 40
		#define CSI2_CLK_SRC 41
		#define ESC0_CLK_SRC 42
		#define ESC1_CLK_SRC 43
		#define GCC_BIMC_GFX_CLK 44
		#define GCC_BIMC_GPU_CLK 45
		#define GCC_BLSP1_AHB_CLK 46
		#define GCC_BLSP1_QUP1_I2C_APPS_CLK 47
		#define GCC_BLSP1_QUP1_SPI_APPS_CLK 48
		#define GCC_BLSP1_QUP2_I2C_APPS_CLK 49
		#define GCC_BLSP1_QUP2_SPI_APPS_CLK 50
		#define GCC_BLSP1_QUP3_I2C_APPS_CLK 51
		#define GCC_BLSP1_QUP3_SPI_APPS_CLK 52
		#define GCC_BLSP1_QUP4_I2C_APPS_CLK 53
		#define GCC_BLSP1_QUP4_SPI_APPS_CLK 54
		#define GCC_BLSP1_UART1_APPS_CLK 55
		#define GCC_BLSP1_UART2_APPS_CLK 56
		#define GCC_BLSP2_QUP1_I2C_APPS_CLK 57
		#define GCC_BLSP2_QUP1_SPI_APPS_CLK 58
		#define GCC_BLSP2_QUP2_I2C_APPS_CLK 59
		#define GCC_BLSP2_QUP2_SPI_APPS_CLK 60
		#define GCC_BLSP2_QUP3_I2C_APPS_CLK 61
		#define GCC_BLSP2_QUP3_SPI_APPS_CLK 62
		#define GCC_BLSP2_QUP4_I2C_APPS_CLK 63
		#define GCC_BLSP2_QUP4_SPI_APPS_CLK 64
		#define GCC_BLSP2_UART1_APPS_CLK 65
		#define GCC_BLSP2_UART2_APPS_CLK 66
		#define GCC_BLSP2_AHB_CLK 67
		#define GCC_BOOT_ROM_AHB_CLK 68
		#define GCC_CAMSS_AHB_CLK 69
		#define GCC_CAMSS_CCI_AHB_CLK 70
		#define GCC_CAMSS_CCI_CLK 71
		#define GCC_CAMSS_CPP_AHB_CLK 72
		#define GCC_CAMSS_CPP_AXI_CLK 73
		#define GCC_CAMSS_CPP_CLK 74
		#define GCC_CAMSS_CSI0_AHB_CLK 75
		#define GCC_CAMSS_CSI0_CLK 76
		#define GCC_CAMSS_CSI0PHY_CLK 77
		#define GCC_CAMSS_CSI0PIX_CLK 78
		#define GCC_CAMSS_CSI0RDI_CLK 79
		#define GCC_CAMSS_CSI1_AHB_CLK 80
		#define GCC_CAMSS_CSI1_CLK 81
		#define GCC_CAMSS_CSI1PHY_CLK 82
		#define GCC_CAMSS_CSI1PIX_CLK 83
		#define GCC_CAMSS_CSI1RDI_CLK 84
		#define GCC_CAMSS_CSI2_AHB_CLK 85
		#define GCC_CAMSS_CSI2_CLK 86
		#define GCC_CAMSS_CSI2PHY_CLK 87
		#define GCC_CAMSS_CSI2PIX_CLK 88
		#define GCC_CAMSS_CSI2RDI_CLK 89
		#define GCC_CAMSS_CSI_VFE0_CLK 90
		#define GCC_CAMSS_GP0_CLK_SRC 91
		#define GCC_CAMSS_GP1_CLK_SRC 92
		#define GCC_CAMSS_CSI_VFE1_CLK 93
		#define GCC_CAMSS_CSI0PHYTIMER_CLK 94
		#define GCC_CAMSS_CSI1PHYTIMER_CLK 95
		#define GCC_CAMSS_GP0_CLK 96
		#define GCC_CAMSS_GP1_CLK 97
		#define GCC_CAMSS_ISPIF_AHB_CLK 98
		#define GCC_CAMSS_JPEG0_CLK 99
		#define GCC_CAMSS_JPEG_AHB_CLK 100
		#define GCC_CAMSS_JPEG_AXI_CLK 101
		#define GCC_CAMSS_MCLK0_CLK 102
		#define GCC_CAMSS_MCLK1_CLK 103
		#define GCC_CAMSS_MCLK2_CLK 104
		#define GCC_CAMSS_MICRO_AHB_CLK 105
		#define GCC_CAMSS_TOP_AHB_CLK 106
		#define GCC_CAMSS_VFE0_CLK 107
		#define GCC_CAMSS_VFE1_AHB_CLK 108
		#define GCC_CAMSS_VFE1_AXI_CLK 109
		#define GCC_CAMSS_VFE1_CLK 110
		#define GCC_CAMSS_VFE_AHB_CLK 111
		#define GCC_CAMSS_VFE_AXI_CLK 112
		#define GCC_CRYPTO_AHB_CLK 113
		#define GCC_CRYPTO_AXI_CLK 114
		#define GCC_CRYPTO_CLK 115
		#define GCC_DCC_CLK 116
		#define GCC_GP1_CLK 117
		#define GCC_GP2_CLK 118
		#define GCC_GP3_CLK 119
		#define GCC_MDSS_AHB_CLK 120
		#define GCC_MDSS_AXI_CLK 121
		#define GCC_MDSS_BYTE0_CLK 122
		#define GCC_MDSS_BYTE1_CLK 123
		#define GCC_MDSS_ESC0_CLK 124
		#define GCC_MDSS_ESC1_CLK 125
		#define GCC_MDSS_MDP_CLK 126
		#define GCC_MDSS_PCLK0_CLK 127
		#define GCC_MDSS_PCLK1_CLK 128
		#define GCC_MDSS_VSYNC_CLK 129
		#define GCC_MSS_CFG_AHB_CLK 130
		#define GCC_MSS_Q6_BIMC_AXI_CLK 131
		#define GCC_OXILI_AHB_CLK 132
		#define GCC_OXILI_AON_CLK 133
		#define GCC_OXILI_GFX3D_CLK 134
		#define GCC_OXILI_TIMER_CLK 135
		#define GCC_PDM2_CLK 136
		#define GCC_PDM_AHB_CLK 137
		#define GCC_PRNG_AHB_CLK 138
		#define GCC_SDCC1_AHB_CLK 139
		#define GCC_SDCC1_APPS_CLK 140
		#define GCC_SDCC1_ICE_CORE_CLK 141
		#define GCC_SDCC2_AHB_CLK 142
		#define GCC_SDCC2_APPS_CLK 143
		#define GCC_USB2A_PHY_SLEEP_CLK 144
		#define GCC_USB_HS_AHB_CLK 145
		#define GCC_USB_HS_PHY_CFG_AHB_CLK 146
		#define GCC_USB_HS_SYSTEM_CLK 147
		#define GCC_VENUS0_AHB_CLK 148
		#define GCC_VENUS0_AXI_CLK 149
		#define GCC_VENUS0_CORE0_VCODEC0_CLK 150
		#define GCC_VENUS0_VCODEC0_CLK 151
		#define GCC_XO_CLK_SRC 152
		#define GFX3D_CLK_SRC 153
		#define GP1_CLK_SRC 154
		#define GP2_CLK_SRC 155
		#define GP3_CLK_SRC 156
		#define JPEG0_CLK_SRC 157
		#define MCLK0_CLK_SRC 158
		#define MCLK1_CLK_SRC 159
		#define MCLK2_CLK_SRC 160
		#define MDP_CLK_SRC 161
		#define MDSS_MDP_VOTE_CLK 162
		#define MDSS_ROTATOR_VOTE_CLK 163
		#define PCLK0_CLK_SRC 164
		#define PCLK1_CLK_SRC 165
		#define PDM2_CLK_SRC 166
		#define SDCC1_APPS_CLK_SRC 167
		#define SDCC1_ICE_CORE_CLK_SRC 168
		#define SDCC2_APPS_CLK_SRC 169
		#define USB_HS_SYSTEM_CLK_SRC 170
		#define VCODEC0_CLK_SRC 171
		#define VFE0_CLK_SRC 172
		#define VFE1_CLK_SRC 173
		#define VSYNC_CLK_SRC 174
		#define GCC_APSS_TCU_CLK 175
		#define GCC_CPP_TBU_CLK 176
		#define GCC_JPEG_TBU_CLK 177
		#define GCC_MDP_TBU_CLK 178
		#define GCC_SMMU_CFG_CLK 179
		#define GCC_VENUS_TBU_CLK 180
		#define GCC_VFE_TBU_CLK 181
		#define GCC_VFE1_TBU_CLK 182
		#define GCC_QDSS_DAP_CLK 183

		/* GCC resets */
		#define GCC_CAMSS_MICRO_BCR 0