msm:ipa3: Fix to reset clk state after before powerup SSR event

Because of updating the current clock state during before 
powerup SSR event causing  invalid clock state due to SSR,
it leads un clock access from IPA Q6. So, changes are
 made to reset clock state to 0.

Change-Id: I9da1b6ad00163d9933a6ccadf0af1e406f5d035c
Acked-by: Praveen Kurapati <pkurapat@qti.qualcomm.com>
Signed-off-by: Mohammed Javid <mjavid@codeaurora.org>