Merge "asoc: codecs: Fix out of bound register access" (25c3a369) · Commits · e / devices / android_kernel_xiaomi_nabu

asoc/codecs/sdm660_cdc/msm-digital-cdc.c

+15 −4

Original line number	Diff line number	Diff line
		@@ -39,6 +39,7 @@
		#define CF_MIN_3DB_75HZ 0x1
		#define CF_MIN_3DB_150HZ 0x2

		#define DEC_SVA 5
		#define MSM_DIG_CDC_VERSION_ENTRY_SIZE 32

		static unsigned long rx_digital_gain_reg[] = {
		@@ -208,6 +209,9 @@ static int msm_dig_cdc_put_dec_enum(struct snd_kcontrol *kcontrol,
		tx_mux_ctl_reg =
		MSM89XX_CDC_CORE_TX1_MUX_CTL + 32 * (decimator - 1);

		if (decimator == DEC_SVA)
		tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX5_MUX_CTL;

		snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x1, adc_dmic_sel);

		ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
		@@ -604,6 +608,9 @@ static void tx_hpf_corner_freq_callback(struct work_struct *work)
		tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL +
		(hpf_work->decimator - 1) * 32;

		if (hpf_work->decimator == DEC_SVA)
		tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX5_MUX_CTL;

		dev_dbg(codec->dev, "%s(): decimator %u hpf_cut_of_freq 0x%x\n",
		__func__, hpf_work->decimator, (unsigned int)hpf_cut_of_freq);
		msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x51);
		@@ -934,7 +941,7 @@ static int msm_dig_cdc_codec_enable_dec(struct snd_soc_dapm_widget *w,
		32 * (decimator - 1);
		tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL +
		32 * (decimator - 1);
		if (decimator == 5) {
		if (decimator == DEC_SVA) {
		tx_vol_ctl_reg = MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG;
		tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX5_MUX_CTL;
		}
		@@ -1245,14 +1252,18 @@ static void sdm660_tx_mute_update_callback(struct work_struct *work)
		dig_cdc = tx_mute_dwork->dig_cdc;
		codec = dig_cdc->codec;

		for (i = 0; i < (NUM_DECIMATORS - 1); i++) {
		for (i = 0; i < NUM_DECIMATORS; i++) {
		if (dig_cdc->dec_active[i])
		decimator = i + 1;
		if (decimator && decimator < NUM_DECIMATORS) {
		if (decimator && decimator <= NUM_DECIMATORS) {
		/* unmute decimators corresponding to Tx DAI's*/
		tx_vol_ctl_reg =
		MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG +
		32 * (decimator - 1);
		if (decimator == DEC_SVA)
		tx_vol_ctl_reg =
		MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG;

		snd_soc_update_bits(codec, tx_vol_ctl_reg,
		0x01, 0x00);
		}