Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 25b489cd authored by Mangesh Kunchamwar's avatar Mangesh Kunchamwar Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: qcom: enable mi2s gpios dynamically in qcs405 



Enable GPIOs for MI2S during usecase setup.

Change-Id: Id4bdb1d2b44c1e7f932883dbcec5005d1378cf98
Signed-off-by: default avatarMangesh Kunchamwar <mangeshk@codeaurora.org>
parent e8d900e1

arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi

+23 −6
Original line number Diff line number Diff line
@@ -43,6 +43,26 @@ 
		pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;

		qcom,lpi-gpios;

	};



	pri_mi2s_gpios: pri_mi2s_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&pri_mi2s_sck_active &pri_mi2s_ws_active

		&pri_mi2s_sd0_active>;

		pinctrl-1 = <&pri_mi2s_sck_sleep &pri_mi2s_ws_sleep

		&pri_mi2s_sd0_sleep>;

	};



	sec_mi2s_gpios: sec_mi2s_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&sec_mi2s_sck_active &sec_mi2s_ws_active

		&sec_mi2s_sd0_active &sec_mi2s_sd1_active

		&sec_mi2s_sd2_active &sec_mi2s_sd3_active>;

		pinctrl-1 = <&sec_mi2s_sck_sleep &sec_mi2s_ws_sleep

		&sec_mi2s_sd0_sleep &sec_mi2s_sd1_sleep

		&sec_mi2s_sd2_sleep &sec_mi2s_sd3_sleep>;

	};

};



&q6core {
@@ -68,6 +88,8 @@ 
	qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;

	qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;

	qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>;

	qcom,pri-mi2s-gpios = <&pri_mi2s_gpios>;

	qcom,sec-mi2s-gpios = <&sec_mi2s_gpios>;

	qcom,audio-routing =

		"RX_BIAS", "MCLK",

		"lineout booster", "LINEOUT1",
@@ -98,12 +120,7 @@ 
		"VA MIC BIAS1", "Digital Mic7",

		"CSRA_12 IN", "PRI_MI2S_RX";

	pinctrl-names = "default";

	pinctrl-0 = <&spdifrx_opt_default

		&pri_mi2s_sck_active &pri_mi2s_ws_active

		&pri_mi2s_sd0_active

		&sec_mi2s_sck_active &sec_mi2s_ws_active

		&sec_mi2s_sd0_active &sec_mi2s_sd1_active

		&sec_mi2s_sd2_active &sec_mi2s_sd3_active>;

	pinctrl-0 = <&spdifrx_opt_default>;

};



&dai_mi2s0 {

arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi

+27 −8
Original line number Diff line number Diff line
@@ -43,6 +43,30 @@ 
		pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;

		qcom,lpi-gpios;

	};



	pri_mi2s_gpios: pri_mi2s_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&pri_mi2s_sck_active &pri_mi2s_ws_active

		&pri_mi2s_sd0_active &pri_mi2s_sd1_active

		&pri_mi2s_sd2_active &pri_mi2s_sd3_active

		&pri_mi2s_sd4_active &pri_mi2s_sd5_active>;

		pinctrl-1 = <&pri_mi2s_sck_sleep &pri_mi2s_ws_sleep

		&pri_mi2s_sd0_sleep &pri_mi2s_sd1_sleep

		&pri_mi2s_sd2_sleep &pri_mi2s_sd3_sleep

		&pri_mi2s_sd4_sleep &pri_mi2s_sd5_sleep>;

	};



	sec_mi2s_gpios: sec_mi2s_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&sec_mi2s_sck_active &sec_mi2s_ws_active

		&sec_mi2s_sd0_active &sec_mi2s_sd1_active

		&sec_mi2s_sd2_active &sec_mi2s_sd3_active>;

		pinctrl-1 = <&sec_mi2s_sck_sleep &sec_mi2s_ws_sleep

		&sec_mi2s_sd0_sleep &sec_mi2s_sd1_sleep

		&sec_mi2s_sd2_sleep &sec_mi2s_sd3_sleep>;

	};

};



&q6core {
@@ -71,6 +95,8 @@ 
	qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;

	qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;

	qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>;

	qcom,pri-mi2s-gpios = <&pri_mi2s_gpios>;

	qcom,sec-mi2s-gpios = <&sec_mi2s_gpios>;

	qcom,audio-routing =

		"RX_BIAS", "MCLK",

		"lineout booster", "LINEOUT1",
@@ -106,14 +132,7 @@ 
		"CSRA_9A IN", "PRI_MI2S_RX",

		"CSRA_BC IN", "PRI_MI2S_RX";

	pinctrl-names = "default";

	pinctrl-0 = <&spdifrx_opt_default

		&pri_mi2s_sck_active &pri_mi2s_ws_active

		&pri_mi2s_sd0_active &pri_mi2s_sd1_active

		&pri_mi2s_sd2_active &pri_mi2s_sd3_active

		&pri_mi2s_sd4_active &pri_mi2s_sd5_active

		&sec_mi2s_sck_active &sec_mi2s_ws_active

		&sec_mi2s_sd0_active &sec_mi2s_sd1_active

		&sec_mi2s_sd2_active &sec_mi2s_sd3_active>;

	pinctrl-0 = <&spdifrx_opt_default>;

};



&dai_mi2s0 {

arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi

+29 −9
Original line number Diff line number Diff line
@@ -43,6 +43,32 @@ 
		pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;

		qcom,lpi-gpios;

	};



	pri_mi2s_gpios: pri_mi2s_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&pri_mi2s_sck_active &pri_mi2s_ws_active

		&pri_mi2s_sd0_active &pri_mi2s_sd1_active

		&pri_mi2s_sd2_active &pri_mi2s_sd3_active

		&pri_mi2s_sd4_active &pri_mi2s_sd5_active

		&pri_mi2s_sd6_active &pri_mi2s_sd7_active>;

		pinctrl-1 = <&pri_mi2s_sck_sleep &pri_mi2s_ws_sleep

		&pri_mi2s_sd0_sleep &pri_mi2s_sd1_sleep

		&pri_mi2s_sd2_sleep &pri_mi2s_sd3_sleep

		&pri_mi2s_sd4_sleep &pri_mi2s_sd5_sleep

		&pri_mi2s_sd6_sleep &pri_mi2s_sd7_sleep>;

	};



	sec_mi2s_gpios: sec_mi2s_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&sec_mi2s_sck_active &sec_mi2s_ws_active

		&sec_mi2s_sd0_active &sec_mi2s_sd1_active

		&sec_mi2s_sd2_active &sec_mi2s_sd3_active>;

		pinctrl-1 = <&sec_mi2s_sck_sleep &sec_mi2s_ws_sleep

		&sec_mi2s_sd0_sleep &sec_mi2s_sd1_sleep

		&sec_mi2s_sd2_sleep &sec_mi2s_sd3_sleep>;

	};

};



&q6core {
@@ -72,6 +98,8 @@ 
	qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;

	qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;

	qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>;

	qcom,pri-mi2s-gpios = <&pri_mi2s_gpios>;

	qcom,sec-mi2s-gpios = <&sec_mi2s_gpios>;

	qcom,audio-routing =

		"RX_BIAS", "MCLK",

		"lineout booster", "LINEOUT1",
@@ -109,15 +137,7 @@ 
		"CSRA_DE IN", "PRI_MI2S_RX",

		"CSRA_F0 IN", "PRI_MI2S_RX";

	pinctrl-names = "default";

	pinctrl-0 = <&spdifrx_opt_default

		&pri_mi2s_sck_active &pri_mi2s_ws_active

		&pri_mi2s_sd0_active &pri_mi2s_sd1_active

		&pri_mi2s_sd2_active &pri_mi2s_sd3_active

		&pri_mi2s_sd4_active &pri_mi2s_sd5_active

		&pri_mi2s_sd6_active &pri_mi2s_sd7_active

		&sec_mi2s_sck_active &sec_mi2s_ws_active

		&sec_mi2s_sd0_active &sec_mi2s_sd1_active

		&sec_mi2s_sd2_active &sec_mi2s_sd3_active>;

	pinctrl-0 = <&spdifrx_opt_default>;

};



&dai_mi2s0 {