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Commit 25a89d91 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: mdss: Separate PP programming to advanced and deferred modes"

parents 985aec5d 280093bb

drivers/media/platform/msm/sde/rotator/sde_rotator_base.h

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
#define SDE_MDP_HW_REV_530	SDE_MDP_REV(5, 3, 0)	/* sm6150 v1.0 */

#define SDE_MDP_HW_REV_540	SDE_MDP_REV(5, 4, 0)	/* sdmtrinket v1.0 */

#define SDE_MDP_HW_REV_620	SDE_MDP_REV(6, 2, 0)	/* atoll */

#define SDE_MDP_HW_REV_320	SDE_MDP_REV(3, 2, 0)	/* sdm660 */



#define SDE_MDP_VBIF_4_LEVEL_REMAPPER	4

#define SDE_MDP_VBIF_8_LEVEL_REMAPPER	8

drivers/media/platform/msm/sde/rotator/sde_rotator_core.c

+2 −0
Original line number Diff line number Diff line
@@ -3127,6 +3127,8 @@ int sde_rotator_core_init(struct sde_rot_mgr **pmgr, 
		mgr->ops_hw_init = sde_rotator_r1_init;

	} else if (IS_SDE_MAJOR_MINOR_SAME(mdata->mdss_version,

			SDE_MDP_HW_REV_300) ||

		IS_SDE_MAJOR_MINOR_SAME(mdata->mdss_version,

			SDE_MDP_HW_REV_320) ||

		IS_SDE_MAJOR_MINOR_SAME(mdata->mdss_version,

			SDE_MDP_HW_REV_400) ||

		IS_SDE_MAJOR_MINOR_SAME(mdata->mdss_version,

drivers/video/fbdev/msm/mdss_debug.c

+3 −1
Original line number Diff line number Diff line
@@ -1470,7 +1470,9 @@ static inline struct mdss_mdp_misr_map *mdss_misr_get_map(u32 block_id, 
						(mdata->mdp_rev ==

							MDSS_MDP_HW_REV_300) ||

						(mdata->mdp_rev ==

							MDSS_MDP_HW_REV_301)) {

							MDSS_MDP_HW_REV_301) ||

						(mdata->mdp_rev ==

							MDSS_MDP_HW_REV_320)) {

						ctrl_reg += 0x8;

						value_reg += 0x8;

					}

drivers/video/fbdev/msm/mdss_mdp.c

+42 −0
Original line number Diff line number Diff line
@@ -2075,6 +2075,48 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) 
		mdata->has_wb_ubwc = true;

		set_bit(MDSS_CAPS_10_BIT_SUPPORTED, mdata->mdss_caps_map);

		break;

	case MDSS_MDP_HW_REV_320:

		mdata->max_target_zorder = 7; /* excluding base layer */

		mdata->max_cursor_size = 512;

		mdata->per_pipe_ib_factor.numer = 8;

		mdata->per_pipe_ib_factor.denom = 5;

		mdata->apply_post_scale_bytes = false;

		mdata->hflip_buffer_reused = false;

		mdata->min_prefill_lines = 25;

		mdata->has_ubwc = true;

		mdata->pixel_ram_size = 50 * 1024;

		mdata->rects_per_sspp[MDSS_MDP_PIPE_TYPE_DMA] = 2;



		//mem_protect_sd_ctrl_id = MEM_PROTECT_SD_CTRL_SWITCH;

		set_bit(MDSS_QOS_PER_PIPE_IB, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_REMAPPER, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_TS_PREFILL, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_OVERHEAD_FACTOR, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_CDP, mdata->mdss_qos_map); /* cdp supported */

		mdata->enable_cdp = false; /* disable cdp */

		set_bit(MDSS_QOS_OTLIM, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_PER_PIPE_LUT, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_SIMPLIFIED_PREFILL, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_TS_PREFILL, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_IB_NOCR, mdata->mdss_qos_map);

		//set_bit(MDSS_QOS_WB2_WRITE_GATHER_EN, mdata->mdss_qos_map);

		set_bit(MDSS_CAPS_YUV_CONFIG, mdata->mdss_caps_map);

		set_bit(MDSS_CAPS_SCM_RESTORE_NOT_REQUIRED,

			mdata->mdss_caps_map);

		set_bit(MDSS_CAPS_3D_MUX_UNDERRUN_RECOVERY_SUPPORTED,

			mdata->mdss_caps_map);

		set_bit(MDSS_CAPS_QSEED3, mdata->mdss_caps_map);

		//set_bit(MDSS_CAPS_MDP_VOTE_CLK_NOT_SUPPORTED,

		//	mdata->mdss_caps_map);

		mdss_mdp_init_default_prefill_factors(mdata);

		mdss_set_quirk(mdata, MDSS_QUIRK_DSC_RIGHT_ONLY_PU);

		mdss_set_quirk(mdata, MDSS_QUIRK_DSC_2SLICE_PU_THRPUT);

		//mdss_set_quirk(mdata, MDSS_QUIRK_MMSS_GDSC_COLLAPSE);

		mdss_set_quirk(mdata, MDSS_QUIRK_MDP_CLK_SET_RATE);

		mdata->has_wb_ubwc = true;

		set_bit(MDSS_CAPS_10_BIT_SUPPORTED, mdata->mdss_caps_map);

		//set_bit(MDSS_CAPS_SEC_DETACH_SMMU, mdata->mdss_caps_map);

		break;

	default:

		mdata->max_target_zorder = 4; /* excluding base layer */

		mdata->max_cursor_size = 64;

drivers/video/fbdev/msm/mdss_mdp.h

+30 −2
Original line number Diff line number Diff line
@@ -94,6 +94,25 @@ 


#define BITS_TO_BYTES(x) DIV_ROUND_UP(x, BITS_PER_BYTE)



#define PP_PROGRAM_PA		0x1

#define PP_PROGRAM_PCC		0x2

#define PP_PROGRAM_IGC		0x4

#define PP_PROGRAM_ARGC	0x8

#define PP_PROGRAM_HIST	0x10

#define PP_PROGRAM_DITHER	0x20

#define PP_PROGRAM_GAMUT	0x40

#define PP_PROGRAM_PGC		0x100

#define PP_PROGRAM_PA_DITHER	0x400

#define PP_PROGRAM_AD		0x800



#define PP_NORMAL_PROGRAM_MASK	(PP_PROGRAM_AD | PP_PROGRAM_PCC | \

				PP_PROGRAM_HIST)

#define PP_DEFER_PROGRAM_MASK	(PP_PROGRAM_IGC | PP_PROGRAM_PGC | \

				PP_PROGRAM_ARGC | PP_PROGRAM_GAMUT | \

				PP_PROGRAM_PA | PP_PROGRAM_DITHER | \

						PP_PROGRAM_PA_DITHER)

#define PP_PROGRAM_ALL	(PP_NORMAL_PROGRAM_MASK | PP_DEFER_PROGRAM_MASK)



enum mdss_mdp_perf_state_type {

	PERF_SW_COMMIT_STATE = 0,

	PERF_HW_MDP_STATE,
@@ -847,6 +866,12 @@ struct mdss_pipe_pp_res { 
	void *hist_lut_cfg_payload;

};



struct mdss_mdp_pp_program_info {

	u32 pp_program_mask;

	u32 pp_opmode_left;

	u32 pp_opmode_right;

};



struct mdss_mdp_pipe_smp_map {

	DECLARE_BITMAP(reserved, MAX_DRV_SUP_MMB_BLKS);

	DECLARE_BITMAP(allocated, MAX_DRV_SUP_MMB_BLKS);
@@ -1322,7 +1347,9 @@ static inline int mdss_mdp_panic_signal_support_mode( 
		IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev,

				MDSS_MDP_HW_REV_116) ||

		IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev,

				MDSS_MDP_HW_REV_117))

				MDSS_MDP_HW_REV_117) ||

		IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev,

				MDSS_MDP_HW_REV_320))

		signal_mode = MDSS_MDP_PANIC_PER_PIPE_CFG;



	return signal_mode;
@@ -1786,7 +1813,8 @@ int mdss_mdp_pp_overlay_init(struct msm_fb_data_type *mfd); 
int mdss_mdp_pp_resume(struct msm_fb_data_type *mfd);



int mdss_mdp_pp_setup(struct mdss_mdp_ctl *ctl);

int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl);

int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl,

				struct mdss_mdp_pp_program_info *info);

int mdss_mdp_pipe_pp_setup(struct mdss_mdp_pipe *pipe, u32 *op);

void mdss_mdp_pipe_pp_clear(struct mdss_mdp_pipe *pipe);

int mdss_mdp_pipe_sspp_setup(struct mdss_mdp_pipe *pipe, u32 *op);