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Commit 24b4b4d9 authored by Krishna Manikandan's avatar Krishna Manikandan Committed by Gerrit - the friendly Code Review server
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drm/msm: update mode2 entry sequence for sde rsc 



Update mode2 entry sequence for sde rsc and change
bwi_threshold with timer slot_0 configuration. This
change also disables the double buffer configuration
before enabling vsync source for video mode display.

Change-Id: Ie85e748035d5c7e1093b002cba22e7cec980cb42
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: default avatarKrishna Manikandan <mkrishn@codeaurora.org>
parent 92569df6

drivers/gpu/drm/msm/sde_rsc.c

+8 −4
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ 


#define RSC_MODE_INSTRUCTION_TIME	100

#define RSC_MODE_THRESHOLD_OVERHEAD	2700

#define MAX_MODE_0_ENTRY_EXIT_TIME	100

#define MIN_THRESHOLD_TIME		0



#define DEFAULT_PANEL_FPS		60

#define DEFAULT_PANEL_JITTER_NUMERATOR	2
@@ -446,9 +446,9 @@ static u32 sde_rsc_timer_calculate(struct sde_rsc_priv *rsc, 
	/* mode 2 is infinite */

	rsc->timer_config.rsc_time_slot_2_ns = 0xFFFFFFFF;



	rsc->timer_config.min_threshold_time_ns = MAX_MODE_0_ENTRY_EXIT_TIME;

	rsc->timer_config.min_threshold_time_ns = MIN_THRESHOLD_TIME;

	rsc->timer_config.bwi_threshold_time_ns =

		rsc->single_tcs_execution_time;

		rsc->timer_config.rsc_time_slot_0_ns;



	/* timer update should be called with client call */

	if (cmd_config && rsc->hw_ops.timer_update) {
@@ -1517,6 +1517,10 @@ static int sde_rsc_probe(struct platform_device *pdev) 
	rsc->mode_threshold_time_ns = rsc->backoff_time_ns

					+ RSC_MODE_THRESHOLD_OVERHEAD;



	if (rsc->version == SDE_RSC_REV_3)

		rsc->time_slot_0_ns = rsc->single_tcs_execution_time

					+ RSC_MODE_INSTRUCTION_TIME;

	else

		rsc->time_slot_0_ns = (rsc->single_tcs_execution_time * 2)

					+ RSC_MODE_INSTRUCTION_TIME;

drivers/gpu/drm/msm/sde_rsc_hw_v3.c

+16 −3
Original line number Diff line number Diff line
@@ -335,7 +335,15 @@ static int sde_rsc_mode2_entry_v3(struct sde_rsc_priv *rsc) 
	if (rsc->power_collapse_block)

		return -EINVAL;



	dss_reg_w(&rsc->wrapper_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,

	if (rsc->sw_fs_enabled) {

		rc = regulator_set_mode(rsc->fs, REGULATOR_MODE_FAST);

		if (rc) {

			pr_err("vdd reg fast mode set failed rc:%d\n", rc);

			return rc;

		}

	}



	dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,

						0x7, rsc->debug_mode);



	for (i = 0; i <= MAX_MODE2_ENTRY_TRY; i++) {
@@ -415,10 +423,15 @@ static int sde_rsc_state_update_v3(struct sde_rsc_priv *rsc, 
	case SDE_RSC_VID_STATE:

		pr_debug("video mode handling\n");



		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_OVERRIDE_CTRL,

							0x0, rsc->debug_mode);

		wmb(); /* disable double buffer config before vsync select */



		ctrl2_config = (rsc->vsync_source & 0x7) << 4;

		ctrl2_config |= (BIT(0) | BIT(1) | BIT(3));

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_OVERRIDE_CTRL2,

				ctrl2_config, rsc->debug_mode);

		wmb(); /* select vsync before double buffer config enabled */



		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_CTRL,

						0x1, rsc->debug_mode);
@@ -519,7 +532,7 @@ static int rsc_hw_bwi_status_v3(struct sde_rsc_priv *rsc, bool bw_indication) 
						0x1, rsc->debug_mode);



	bw_ack = dss_reg_r(&rsc->wrapper_io, SDE_RSCC_WRAPPER_DEBUG_CTRL2,

			rsc->debug_mode) & BIT(13);

			rsc->debug_mode) & BIT(14);



	/* check for sequence running status before exiting */

	for (count = MAX_CHECK_LOOPS; count > 0 && !bw_ack; count--) {
@@ -528,7 +541,7 @@ static int rsc_hw_bwi_status_v3(struct sde_rsc_priv *rsc, bool bw_indication) 
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_BW_INDICATION,

						bw_indication, rsc->debug_mode);

		bw_ack = dss_reg_r(&rsc->wrapper_io,

		       SDE_RSCC_WRAPPER_DEBUG_CTRL2, rsc->debug_mode) & BIT(13);

		       SDE_RSCC_WRAPPER_DEBUG_CTRL2, rsc->debug_mode) & BIT(14);

	}



	if (!bw_ack)