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Unverified Commit 24a95f75 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
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clk: sunxi-ng: r40: Add minimal rate for video PLLs 



According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.

Because of that, set minimal rate to both R40 video PLLs to 192 MHz.

Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent ce397d21

drivers/clk/sunxi-ng/ccu-sun8i-r40.c

+24 −22
Original line number Diff line number Diff line
@@ -66,8 +66,9 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 
				   CLK_SET_RATE_UNGATE);



/* TODO: The result of N/M is required to be in [8, 25] range. */

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",

					    "osc24M", 0x0010,

					    192000000,	/* Minimum rate */

					    8, 7,	/* N */

					    0, 4,	/* M */

					    BIT(24),	/* frac enable */
@@ -152,8 +153,9 @@ static struct ccu_nk pll_periph1_clk = { 
};



/* TODO: The result of N/M is required to be in [8, 25] range. */

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",

					    "osc24M", 0x030,

					    192000000,	/* Minimum rate */

					    8, 7,	/* N */

					    0, 4,	/* M */

					    BIT(24),	/* frac enable */