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Commit 2468dcf6 authored by Ian Munsie's avatar Ian Munsie Committed by Benjamin Herrenschmidt
Browse files

powerpc: Add support for context switching the TAR register 



This patch adds support for enabling and context switching the Target
Address Register in Power8. The TAR is a new special purpose register
that can be used for computed branches with the bctar[l] (branch
conditional to TAR) instruction in the same manner as the count and link
registers.

Signed-off-by: default avatarIan Munsie <imunsie@au1.ibm.com>
Signed-off-by: default avatarMatt Evans <matt@ozlabs.org>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 14b6f00f

arch/powerpc/include/asm/cputable.h

+1 −1
Original line number Diff line number Diff line
@@ -414,7 +414,7 @@ extern const char *powerpc_base_platform; 
	    CPU_FTR_DSCR | CPU_FTR_SAO  | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \

	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR)

	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | CPU_FTR_BCTAR)

#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

arch/powerpc/include/asm/processor.h

+3 −0
Original line number Diff line number Diff line
@@ -257,6 +257,9 @@ struct thread_struct { 
	int		dscr_inherit;

	unsigned long	ppr;	/* used to save/restore SMT priority */

#endif

#ifdef CONFIG_PPC_BOOK3S_64

	unsigned long	tar;

#endif

};



#define ARCH_MIN_TASKALIGN 16

arch/powerpc/include/asm/reg.h

+3 −0
Original line number Diff line number Diff line
@@ -237,6 +237,9 @@ 
#define SPRN_HRMOR	0x139	/* Real mode offset register */

#define SPRN_HSRR0	0x13A	/* Hypervisor Save/Restore 0 */

#define SPRN_HSRR1	0x13B	/* Hypervisor Save/Restore 1 */

#define SPRN_FSCR	0x099	/* Facility Status & Control Register */

#define FSCR_TAR	(1<<8)	/* Enable Target Adress Register */

#define SPRN_TAR	0x32f	/* Target Address Register */

#define SPRN_LPCR	0x13E	/* LPAR Control Register */

#define   LPCR_VPM0	(1ul << (63-0))

#define   LPCR_VPM1	(1ul << (63-1))

arch/powerpc/kernel/asm-offsets.c

+4 −0
Original line number Diff line number Diff line
@@ -122,6 +122,10 @@ int main(void) 
	DEFINE(THREAD_KVM_VCPU, offsetof(struct thread_struct, kvm_vcpu));

#endif



#ifdef CONFIG_PPC_BOOK3S_64

	DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar));

#endif



	DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));

	DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags));

	DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));

arch/powerpc/kernel/cpu_setup_power.S

+7 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ _GLOBAL(__setup_cpu_power8) 
	mfspr	r3,SPRN_LPCR

	oris	r3, r3, LPCR_AIL_3@h

	bl	__init_LPCR

	bl	__init_FSCR

	bl	__init_TLB

	mtlr	r11

	blr
@@ -112,6 +113,12 @@ __init_LPCR: 
	isync

	blr



__init_FSCR:

	mfspr	r3,SPRN_FSCR

	ori	r3,r3,FSCR_TAR

	mtspr	SPRN_FSCR,r3

	blr



__init_TLB:

	/* Clear the TLB */

	li	r6,128