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Commit 229be9c1 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Shawn Guo
Browse files

ARM: i.MX clk: Move clock check function in common location 



This patch moves clock check function in common i.MX location
and switch i.MX clk drivers to use this new function.

Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent c349adde

arch/arm/mach-imx/clk-imx1.c

+1 −6
Original line number Diff line number Diff line
@@ -44,8 +44,6 @@ static void __iomem *ccm __initdata; 


static void __init _mx1_clocks_init(unsigned long fref)

{

	unsigned i;



	clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);

	clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);

	clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
@@ -72,10 +70,7 @@ static void __init _mx1_clocks_init(unsigned long fref) 
	clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);

	clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);



	for (i = 0; i < ARRAY_SIZE(clk); i++)

		if (IS_ERR(clk[i]))

			pr_err("imx1 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));

	imx_check_clocks(clk, ARRAY_SIZE(clk));

}



int __init mx1_clocks_init(unsigned long fref)

arch/arm/mach-imx/clk-imx21.c

+1 −6
Original line number Diff line number Diff line
@@ -70,8 +70,6 @@ static struct clk *clk[clk_max]; 
 */

int __init mx21_clocks_init(unsigned long lref, unsigned long href)

{

	int i;



	clk[ckil] = imx_clk_fixed("ckil", lref);

	clk[ckih] = imx_clk_fixed("ckih", href);

	clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
@@ -126,10 +124,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) 
	clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);

	clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);



	for (i = 0; i < ARRAY_SIZE(clk); i++)

		if (IS_ERR(clk[i]))

			pr_err("i.MX21 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));

	imx_check_clocks(clk, ARRAY_SIZE(clk));



	clk_register_clkdev(clk[per1], "per1", NULL);

	clk_register_clkdev(clk[per2], "per2", NULL);

arch/arm/mach-imx/clk-imx25.c

+1 −6
Original line number Diff line number Diff line
@@ -93,8 +93,6 @@ static struct clk *clk[clk_max]; 


static int __init __mx25_clocks_init(unsigned long osc_rate)

{

	int i;



	clk[dummy] = imx_clk_fixed("dummy", 0);

	clk[osc] = imx_clk_fixed("osc", osc_rate);

	clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
@@ -224,10 +222,7 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) 
	/* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */

	clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);



	for (i = 0; i < ARRAY_SIZE(clk); i++)

		if (IS_ERR(clk[i]))

			pr_err("i.MX25 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));

	imx_check_clocks(clk, ARRAY_SIZE(clk));



	clk_prepare_enable(clk[emi_ahb]);

arch/arm/mach-imx/clk-imx27.c

+1 −6
Original line number Diff line number Diff line
@@ -90,8 +90,6 @@ static struct clk_onecell_data clk_data; 


static void __init _mx27_clocks_init(unsigned long fref)

{

	unsigned i;



	BUG_ON(!ccm);



	clk[dummy] = imx_clk_fixed("dummy", 0);
@@ -201,10 +199,7 @@ static void __init _mx27_clocks_init(unsigned long fref) 
	clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);

	clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);



	for (i = 0; i < ARRAY_SIZE(clk); i++)

		if (IS_ERR(clk[i]))

			pr_err("i.MX27 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));

	imx_check_clocks(clk, ARRAY_SIZE(clk));



	clk_register_clkdev(clk[cpu_div], NULL, "cpu0");

arch/arm/mach-imx/clk-imx31.c

+1 −5
Original line number Diff line number Diff line
@@ -51,7 +51,6 @@ static struct clk_onecell_data clk_data; 
int __init mx31_clocks_init(unsigned long fref)

{

	void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);

	int i;

	struct device_node *np;



	clk[dummy] = imx_clk_fixed("dummy", 0);
@@ -114,10 +113,7 @@ int __init mx31_clocks_init(unsigned long fref) 
	clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);

	clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);



	for (i = 0; i < ARRAY_SIZE(clk); i++)

		if (IS_ERR(clk[i]))

			pr_err("imx31 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));

	imx_check_clocks(clk, ARRAY_SIZE(clk));



	np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");