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Commit 22983c30 authored by Vivek Natarajan's avatar Vivek Natarajan Committed by John W. Linville
Browse files

ath9k_hw: DDR_PLL and BB_PLL need correct setting. 



Updates from the analog team for AR9485 chipsets to set
DDR_PLL2 and DDR_PLL3. Also program the BB_PLL ki
and kd value.

Signed-off-by: default avatarVivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 181fb18d

drivers/net/wireless/ath/ath9k/hw.c

+25 −1
Original line number Diff line number Diff line
@@ -681,13 +681,37 @@ unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 
}

EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);



#define DPLL2_KD_VAL            0x3D

#define DPLL2_KI_VAL            0x06

#define DPLL3_PHASE_SHIFT_VAL   0x1



static void ath9k_hw_init_pll(struct ath_hw *ah,

			      struct ath9k_channel *chan)

{

	u32 pll;



	if (AR_SREV_9485(ah))

	if (AR_SREV_9485(ah)) {

		REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);

		REG_WRITE(ah, AR_CH0_DDR_DPLL2, 0x19e82f01);



		REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,

			      AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);



		REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);

		udelay(100);



		REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);



		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,

			      AR_CH0_DPLL2_KD, DPLL2_KD_VAL);

		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,

			      AR_CH0_DPLL2_KI, DPLL2_KI_VAL);



		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,

			      AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);

		REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);

		udelay(110);

	}



	pll = ath9k_hw_compute_pll_control(ah, chan);

drivers/net/wireless/ath/ath9k/reg.h

+11 −0
Original line number Diff line number Diff line
@@ -1083,6 +1083,17 @@ enum { 
#define AR_ENT_OTP		  0x40d8

#define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000

#define AR_ENT_OTP_MPSD		0x00800000

#define AR_CH0_BB_DPLL2          0x16184

#define AR_CH0_BB_DPLL3          0x16188

#define AR_CH0_DDR_DPLL2         0x16244

#define AR_CH0_DDR_DPLL3         0x16248

#define AR_CH0_DPLL2_KD              0x03F80000

#define AR_CH0_DPLL2_KD_S            19

#define AR_CH0_DPLL2_KI              0x3C000000

#define AR_CH0_DPLL2_KI_S            26

#define AR_CH0_DPLL3_PHASE_SHIFT     0x3F800000

#define AR_CH0_DPLL3_PHASE_SHIFT_S   23

#define AR_PHY_CCA_NOM_VAL_2GHZ      -118



#define AR_RTC_9300_PLL_DIV          0x000003ff

#define AR_RTC_9300_PLL_DIV_S        0