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Commit 22721881 authored by Justin Swartz's avatar Justin Swartz Committed by Greg Kroah-Hartman
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clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocks 



commit cec9d101d70a3509da9bd2e601e0b242154ce616 upstream.

The following changes prevent the unrecoverable freezes and rcu_sched
stall warnings experienced in each of my attempts to take advantage of
lima.

Replace the COMPOSITE_NOGATE definition of aclk_gpu_pre with a
COMPOSITE that retains the selection of HDMIPHY as the PLL source, but
instead makes uses of the aclk_gpu PLL source gate and parent names
defined by mux_pll_src_4plls_p rather than mux_aclk_gpu_pre_p.

Remove the now unused mux_aclk_gpu_pre_p and the four named but also
unused definitions (cpll_gpu, gpll_gpu, hdmiphy_gpu and usb480m_gpu)
of the aclk_gpu PLL source gate.

Use the correct gate offset for aclk_gpu and aclk_gpu_noc.

Fixes: 307a2e9a ("clk: rockchip: add clock controller for rk3228")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarJustin Swartz <justin.swartz@risingedge.co.za>
[double-checked against SoC manual and added fixes tag]
Link: https://lore.kernel.org/r/20200114162503.7548-1-justin.swartz@risingedge.co.za


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c5768e0a

drivers/clk/rockchip/clk-rk3228.c

+4 −13
Original line number Diff line number Diff line
@@ -163,8 +163,6 @@ PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; 
PNAME(mux_i2s2_p)		= { "i2s2_src", "i2s2_frac", "xin12m" };

PNAME(mux_sclk_spdif_p)		= { "sclk_spdif_src", "spdif_frac", "xin12m" };



PNAME(mux_aclk_gpu_pre_p)	= { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" };



PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };

PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };

PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
@@ -475,16 +473,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
			RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,

			RK2928_CLKGATE_CON(2), 8, GFLAGS),



	GATE(0, "cpll_gpu", "cpll", 0,

			RK2928_CLKGATE_CON(3), 13, GFLAGS),

	GATE(0, "gpll_gpu", "gpll", 0,

			RK2928_CLKGATE_CON(3), 13, GFLAGS),

	GATE(0, "hdmiphy_gpu", "hdmiphy", 0,

			RK2928_CLKGATE_CON(3), 13, GFLAGS),

	GATE(0, "usb480m_gpu", "usb480m", 0,

	COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_4plls_p, 0,

			RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS,

			RK2928_CLKGATE_CON(3), 13, GFLAGS),

	COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0,

			RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS),



	COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,

			RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
@@ -589,8 +580,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
	GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),



	/* PD_GPU */

	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),

	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),

	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),

	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),



	/* PD_BUS */

	GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),