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Commit 21315046 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add dummy clock support for SDM855 



Add the dummy clock nodes and the headers for clients to
use to get their respective clock handles.

Change-Id: Ia7def37be29e1a658a4b1bc03b7c971eb4925c91
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent bb0e3212

arch/arm64/boot/dts/qcom/sdm855.dtsi

+64 −0
Original line number Diff line number Diff line
@@ -11,6 +11,14 @@ 
 */



#include "skeleton64.dtsi"

#include <dt-bindings/clock/qcom,gcc-sdm855.h>

#include <dt-bindings/clock/qcom,camcc-sdm855.h>

#include <dt-bindings/clock/qcom,dispcc-sdm855.h>

#include <dt-bindings/clock/qcom,gpucc-sdm855.h>

#include <dt-bindings/clock/qcom,videocc-sdm855.h>

#include <dt-bindings/clock/qcom,cpucc-sdm855.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,aop-qmp.h>



/ {

	model = "Qualcomm Technologies, Inc. SDM855";
@@ -282,4 +290,60 @@ 
			status = "disabled";

		};

	};



	clock_rpmh: qcom,rpmhclk {

		compatible = "qcom,dummycc";

		clock-output-names = "rpm_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_aop: qcom,aopclk {

		compatible = "qcom,dummycc";

		clock-output-names = "aop_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_gcc: qcom,gcc {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_videocc: qcom,videocc {

		compatible = "qcom,dummycc";

		clock-output-names = "videocc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_camcc: qcom,camcc {

		compatible = "qcom,dummycc";

		clock-output-names = "camcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_dispcc: qcom,dispcc {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_gpucc: qcom,dispcc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_cpucc: qcom,cpucc {

		compatible = "qcom,dummycc";

		clock-output-names = "cpucc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

};

include/dt-bindings/clock/qcom,aop-qmp.h

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Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_AOP_QMP_H

#define _DT_BINDINGS_CLK_QCOM_AOP_QMP_H



#define QDSS_CLK_LEVEL_OFF		0

#define QDSS_CLK_LEVEL_DYNAMIC		1

#define QDSS_CLK_LEVEL_TURBO		2

#define QDSS_CLK_LEVEL_NOMINAL		3

#define QDSS_CLK_LEVEL_SVS_L1		4

#define QDSS_CLK_LEVEL_SVS		5

#define QDSS_CLK_LEVEL_LOW_SVS		6

#define QDSS_CLK_LEVEL_MIN_SVS		7



/* clocks id */

#define QDSS_CLK			0



#endif

include/dt-bindings/clock/qcom,camcc-sdm855.h

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+138 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SDM855_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SDM855_H



#define CAM_CC_BPS_AHB_CLK					0

#define CAM_CC_BPS_AREG_CLK					1

#define CAM_CC_BPS_AXI_CLK					2

#define CAM_CC_BPS_CLK						3

#define CAM_CC_BPS_CLK_SRC					4

#define CAM_CC_CAMNOC_AXI_CLK					5

#define CAM_CC_CAMNOC_AXI_CLK_SRC				6

#define CAM_CC_CAMNOC_DCD_XO_CLK				7

#define CAM_CC_CCI_0_CLK					8

#define CAM_CC_CCI_0_CLK_SRC					9

#define CAM_CC_CCI_1_CLK					10

#define CAM_CC_CCI_1_CLK_SRC					11

#define CAM_CC_CORE_AHB_CLK					12

#define CAM_CC_CPAS_AHB_CLK					13

#define CAM_CC_CPHY_RX_CLK_SRC					14

#define CAM_CC_CSI0PHYTIMER_CLK					15

#define CAM_CC_CSI0PHYTIMER_CLK_SRC				16

#define CAM_CC_CSI1PHYTIMER_CLK					17

#define CAM_CC_CSI1PHYTIMER_CLK_SRC				18

#define CAM_CC_CSI2PHYTIMER_CLK					19

#define CAM_CC_CSI2PHYTIMER_CLK_SRC				20

#define CAM_CC_CSI3PHYTIMER_CLK					21

#define CAM_CC_CSI3PHYTIMER_CLK_SRC				22

#define CAM_CC_CSIPHY0_CLK					23

#define CAM_CC_CSIPHY1_CLK					24

#define CAM_CC_CSIPHY2_CLK					25

#define CAM_CC_CSIPHY3_CLK					26

#define CAM_CC_FAST_AHB_CLK_SRC					27

#define CAM_CC_FD_CORE_CLK					28

#define CAM_CC_FD_CORE_CLK_SRC					29

#define CAM_CC_FD_CORE_UAR_CLK					30

#define CAM_CC_GDSC_CLK						31

#define CAM_CC_ICP_AHB_CLK					32

#define CAM_CC_ICP_CLK						33

#define CAM_CC_ICP_CLK_SRC					34

#define CAM_CC_IFE_0_AXI_CLK					35

#define CAM_CC_IFE_0_CLK					36

#define CAM_CC_IFE_0_CLK_SRC					37

#define CAM_CC_IFE_0_CPHY_RX_CLK				38

#define CAM_CC_IFE_0_CSID_CLK					39

#define CAM_CC_IFE_0_CSID_CLK_SRC				40

#define CAM_CC_IFE_0_DSP_CLK					41

#define CAM_CC_IFE_1_AXI_CLK					42

#define CAM_CC_IFE_1_CLK					43

#define CAM_CC_IFE_1_CLK_SRC					44

#define CAM_CC_IFE_1_CPHY_RX_CLK				45

#define CAM_CC_IFE_1_CSID_CLK					46

#define CAM_CC_IFE_1_CSID_CLK_SRC				47

#define CAM_CC_IFE_1_DSP_CLK					48

#define CAM_CC_IFE_LITE_0_CLK					49

#define CAM_CC_IFE_LITE_0_CLK_SRC				50

#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK				51

#define CAM_CC_IFE_LITE_0_CSID_CLK				52

#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC				53

#define CAM_CC_IFE_LITE_1_CLK					54

#define CAM_CC_IFE_LITE_1_CLK_SRC				55

#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK				56

#define CAM_CC_IFE_LITE_1_CSID_CLK				57

#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC				58

#define CAM_CC_IPE_0_AHB_CLK					59

#define CAM_CC_IPE_0_AREG_CLK					60

#define CAM_CC_IPE_0_AXI_CLK					61

#define CAM_CC_IPE_0_CLK					62

#define CAM_CC_IPE_0_CLK_SRC					63

#define CAM_CC_IPE_1_AHB_CLK					64

#define CAM_CC_IPE_1_AREG_CLK					65

#define CAM_CC_IPE_1_AXI_CLK					66

#define CAM_CC_IPE_1_CLK					67

#define CAM_CC_JPEG_CLK						68

#define CAM_CC_JPEG_CLK_SRC					69

#define CAM_CC_LRME_CLK						70

#define CAM_CC_LRME_CLK_SRC					71

#define CAM_CC_MCLK0_CLK					72

#define CAM_CC_MCLK0_CLK_SRC					73

#define CAM_CC_MCLK1_CLK					74

#define CAM_CC_MCLK1_CLK_SRC					75

#define CAM_CC_MCLK2_CLK					76

#define CAM_CC_MCLK2_CLK_SRC					77

#define CAM_CC_MCLK3_CLK					78

#define CAM_CC_MCLK3_CLK_SRC					79

#define CAM_CC_PLL0						80

#define CAM_CC_PLL0_OUT_EVEN					81

#define CAM_CC_PLL0_OUT_ODD					82

#define CAM_CC_PLL1						83

#define CAM_CC_PLL1_OUT_EVEN					84

#define CAM_CC_PLL2						85

#define CAM_CC_PLL2_OUT_MAIN					86

#define CAM_CC_PLL3						87

#define CAM_CC_PLL3_OUT_EVEN					88

#define CAM_CC_PLL4						89

#define CAM_CC_PLL4_OUT_EVEN					90

#define CAM_CC_PLL_TEST_CLK					91

#define CAM_CC_QDSS_DEBUG_CLK					92

#define CAM_CC_QDSS_DEBUG_CLK_SRC				93

#define CAM_CC_QDSS_DEBUG_XO_CLK				94

#define CAM_CC_SLOW_AHB_CLK_SRC					95



#define CAM_CC_BPS_BCR						0

#define CAM_CC_CAMNOC_BCR					1

#define CAM_CC_CCI_BCR						2

#define CAM_CC_CPAS_BCR						3

#define CAM_CC_CSI0PHY_BCR					4

#define CAM_CC_CSI1PHY_BCR					5

#define CAM_CC_CSI2PHY_BCR					6

#define CAM_CC_CSI3PHY_BCR					7

#define CAM_CC_FD_BCR						8

#define CAM_CC_ICP_BCR						9

#define CAM_CC_IFE_0_BCR					10

#define CAM_CC_IFE_1_BCR					11

#define CAM_CC_IFE_LITE_0_BCR					12

#define CAM_CC_IFE_LITE_1_BCR					13

#define CAM_CC_IPE_0_BCR					14

#define CAM_CC_IPE_1_BCR					15

#define CAM_CC_JPEG_BCR						16

#define CAM_CC_LRME_BCR						17

#define CAM_CC_MCLK0_BCR					18

#define CAM_CC_MCLK1_BCR					19

#define CAM_CC_MCLK2_BCR					20

#define CAM_CC_MCLK3_BCR					21

#define CAM_CC_QDSS_DEBUG_BCR					22



#endif

include/dt-bindings/clock/qcom,cpucc-sdm855.h

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Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_CPU_CC_SDM855_H

#define _DT_BINDINGS_CLK_QCOM_CPU_CC_SDM855_H



#define L3_CLUSTER0_VOTE_CLK					0

#define L3_CLUSTER1_VOTE_CLK					1

#define L3_CLK							2

#define CPU0_PWRCL_CLK						3

#define CPU1_PWRCL_CLK						4

#define CPU2_PWRCL_CLK						5

#define CPU3_PWRCL_CLK						6

#define PWRCL_CLK						7

#define CPU4_PERFCL_CLK						8

#define CPU5_PERFCL_CLK						9

#define CPU6_PERFCL_CLK						10

#define CPU7_PERFCL_CLK						11

#define PERFCL_CLK						12



#endif

include/dt-bindings/clock/qcom,dispcc-sdm855.h

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Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SDM855_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SDM855_H



#define DISP_CC_MDSS_AHB_CLK					0

#define DISP_CC_MDSS_AHB_CLK_SRC				1

#define DISP_CC_MDSS_BYTE0_CLK					2

#define DISP_CC_MDSS_BYTE0_CLK_SRC				3

#define DISP_CC_MDSS_BYTE0_INTF_CLK				4

#define DISP_CC_MDSS_BYTE1_CLK					5

#define DISP_CC_MDSS_BYTE1_CLK_SRC				6

#define DISP_CC_MDSS_BYTE1_INTF_CLK				7

#define DISP_CC_MDSS_DP_AUX1_CLK				8

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				9

#define DISP_CC_MDSS_DP_AUX_CLK					10

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				11

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				12

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				13

#define DISP_CC_MDSS_DP_CRYPTO_CLK				14

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				15

#define DISP_CC_MDSS_DP_LINK1_CLK				16

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				17

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				18

#define DISP_CC_MDSS_DP_LINK_CLK				19

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				20

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				21

#define DISP_CC_MDSS_DP_PIXEL1_CLK				22

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				23

#define DISP_CC_MDSS_DP_PIXEL2_CLK				24

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				25

#define DISP_CC_MDSS_DP_PIXEL_CLK				26

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				27

#define DISP_CC_MDSS_EDP_AUX_CLK				28

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				29

#define DISP_CC_MDSS_EDP_GTC_CLK				30

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				31

#define DISP_CC_MDSS_EDP_LINK_CLK				32

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				33

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				34

#define DISP_CC_MDSS_EDP_PIXEL_CLK				35

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				36

#define DISP_CC_MDSS_ESC0_CLK					37

#define DISP_CC_MDSS_ESC0_CLK_SRC				38

#define DISP_CC_MDSS_ESC1_CLK					39

#define DISP_CC_MDSS_ESC1_CLK_SRC				40

#define DISP_CC_MDSS_MDP_CLK					41

#define DISP_CC_MDSS_MDP_CLK_SRC				42

#define DISP_CC_MDSS_MDP_LUT_CLK				43

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				44

#define DISP_CC_MDSS_PCLK0_CLK					45

#define DISP_CC_MDSS_PCLK0_CLK_SRC				46

#define DISP_CC_MDSS_PCLK1_CLK					47

#define DISP_CC_MDSS_PCLK1_CLK_SRC				48

#define DISP_CC_MDSS_ROT_CLK					49

#define DISP_CC_MDSS_ROT_CLK_SRC				50

#define DISP_CC_MDSS_RSCC_AHB_CLK				51

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				52

#define DISP_CC_MDSS_VSYNC_CLK					53

#define DISP_CC_MDSS_VSYNC_CLK_SRC				54

#define DISP_CC_PLL0						55

#define DISP_CC_PLL1						56

#define DISP_CC_PLL_TEST_CLK					57



#define DISP_CC_MDSS_CORE_BCR					0

#define DISP_CC_MDSS_RSCC_BCR					1

#define DISP_CC_MDSS_SPDM_BCR					2



#endif