Commit 20dd4c62 authored Jul 11, 2017 by Madhavan Srinivasan Committed by Michael Ellerman Jul 11, 2017

powerpc/perf: Fix SDAR_MODE value for continous sampling on Power9



In case of continous sampling (non-marked), the code currently
sets MMCRA[SDAR_MODE] to 0b01 (Update on TLB miss) for Power9 DD1.

On DD2 and later it copies the sdar_mode value from the event code,
which for most events is 0b00 (No updates).

However we must set a non-zero value for SDAR_MODE when doing
continuous sampling, so honor the event code, unless it's zero, in
which case we use use 0b01 (Update on TLB miss).

Fixes: 78b4416a ("powerpc/perf: Handle sdar_mode for marked event in power9")
Cc: stable@vger.kernel.org # v4.11+
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent 2400fd82

arch/powerpc/perf/isa207-common.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -90,13 +90,15 @@ static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
		* MMCRA[SDAR_MODE] will be set to 0b01
		* For rest
		* MMCRA[SDAR_MODE] will be set from event code.
		* If sdar_mode from event is zero, default to 0b01. Hardware
		* requires that we set a non-zero value.
		*/
		if (cpu_has_feature(CPU_FTR_ARCH_300)) {
		if (is_event_marked(event) \|\| (*mmcra & MMCRA_SAMPLE_ENABLE))
		*mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
		else if (!cpu_has_feature(CPU_FTR_POWER9_DD1))
		else if (!cpu_has_feature(CPU_FTR_POWER9_DD1) && p9_SDAR_MODE(event))
		*mmcra \|= p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
		else if (cpu_has_feature(CPU_FTR_POWER9_DD1))
		else
		*mmcra \|= MMCRA_SDAR_MODE_TLB;
		} else
		*mmcra \|= MMCRA_SDAR_MODE_TLB;