Merge "coresight-tmc: Add support of pcie mode" (206e8052) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/hwtracing/coresight/coresight-byte-cntr.c

+216 −4

Original line number	Diff line number	Diff line
		/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -16,11 +16,14 @@
		#include <linux/moduleparam.h>
		#include <linux/delay.h>
		#include <linux/uaccess.h>
		#include <linux/slab.h>

		#include "coresight-byte-cntr.h"
		#include "coresight-priv.h"
		#include "coresight-tmc.h"

		#define PCIE_BLK_SIZE 32768

		static struct tmc_drvdata *tmcdrvdata;

		static void tmc_etr_read_bytes(struct byte_cntr byte_cntr_data, loff_t ppos,
		@@ -119,9 +122,13 @@ static irqreturn_t etr_handler(int irq, void *data)
		{
		struct byte_cntr *byte_cntr_data = data;

		if (tmcdrvdata->out_mode == TMC_ETR_OUT_MODE_MEM) {
		atomic_inc(&byte_cntr_data->irq_cnt);

		wake_up(&byte_cntr_data->wq);
		} else if (tmcdrvdata->out_mode == TMC_ETR_OUT_MODE_PCIE) {
		atomic_inc(&byte_cntr_data->irq_cnt);
		wake_up(&byte_cntr_data->pcie_wait_wq);
		}

		return IRQ_HANDLED;
		}
		@@ -261,6 +268,49 @@ void tmc_etr_byte_cntr_stop(struct byte_cntr *byte_cntr_data)
		}
		EXPORT_SYMBOL(tmc_etr_byte_cntr_stop);

		static void etr_pcie_close_channel(struct byte_cntr *byte_cntr_data)
		{
		if (!byte_cntr_data)
		return;

		mutex_lock(&byte_cntr_data->byte_cntr_lock);
		mhi_dev_close_channel(byte_cntr_data->out_handle);
		byte_cntr_data->pcie_chan_opened = false;
		mutex_unlock(&byte_cntr_data->byte_cntr_lock);
		}

		int etr_pcie_start(struct byte_cntr *byte_cntr_data)
		{
		if (!byte_cntr_data)
		return -ENOMEM;

		mutex_lock(&byte_cntr_data->byte_cntr_lock);
		coresight_csr_set_byte_cntr(byte_cntr_data->csr, PCIE_BLK_SIZE / 8);
		atomic_set(&byte_cntr_data->irq_cnt, 0);
		mutex_unlock(&byte_cntr_data->byte_cntr_lock);

		if (!byte_cntr_data->pcie_chan_opened)
		queue_work(byte_cntr_data->pcie_wq,
		&byte_cntr_data->pcie_open_work);

		queue_work(byte_cntr_data->pcie_wq, &byte_cntr_data->pcie_write_work);
		return 0;
		}
		EXPORT_SYMBOL(etr_pcie_start);

		void etr_pcie_stop(struct byte_cntr *byte_cntr_data)
		{
		if (!byte_cntr_data)
		return;

		etr_pcie_close_channel(byte_cntr_data);
		wake_up(&byte_cntr_data->pcie_wait_wq);

		mutex_lock(&byte_cntr_data->byte_cntr_lock);
		coresight_csr_set_byte_cntr(byte_cntr_data->csr, 0);
		mutex_unlock(&byte_cntr_data->byte_cntr_lock);
		}
		EXPORT_SYMBOL(etr_pcie_stop);

		static int tmc_etr_byte_cntr_release(struct inode in, struct file fp)
		{
		@@ -358,6 +408,167 @@ static int byte_cntr_register_chardev(struct byte_cntr *byte_cntr_data)
		return ret;
		}

		static void etr_pcie_client_cb(struct mhi_dev_client_cb_data *cb_data)
		{
		struct byte_cntr *byte_cntr_data = NULL;

		if (!cb_data)
		return;

		byte_cntr_data = cb_data->user_data;
		if (!byte_cntr_data)
		return;

		switch (cb_data->ctrl_info) {
		case MHI_STATE_CONNECTED:
		if (cb_data->channel == byte_cntr_data->pcie_out_chan) {
		dev_dbg(tmcdrvdata->dev, "PCIE out channel connected.\n");
		queue_work(byte_cntr_data->pcie_wq,
		&byte_cntr_data->pcie_open_work);
		}

		break;
		case MHI_STATE_DISCONNECTED:
		if (cb_data->channel == byte_cntr_data->pcie_out_chan) {
		dev_dbg(tmcdrvdata->dev, "PCIE out channel disconnected.\n");
		etr_pcie_close_channel(byte_cntr_data);
		}
		break;
		default:
		break;
		}
		}

		static void etr_pcie_write_complete_cb(void *req)
		{
		struct mhi_req *mreq = req;

		if (!mreq)
		return;
		kfree(req);
		}

		static void etr_pcie_open_work_fn(struct work_struct *work)
		{
		int ret = 0;
		struct byte_cntr *byte_cntr_data = container_of(work,
		struct byte_cntr,
		pcie_open_work);

		if (!byte_cntr_data)
		return;

		/* Open write channel*/
		ret = mhi_dev_open_channel(byte_cntr_data->pcie_out_chan,
		&byte_cntr_data->out_handle,
		NULL);
		if (ret < 0) {
		dev_err(tmcdrvdata->dev, "%s: open pcie out channel fail %d\n",
		__func__, ret);
		} else {
		dev_dbg(tmcdrvdata->dev,
		"Open pcie out channel successfully\n");
		mutex_lock(&byte_cntr_data->byte_cntr_lock);
		byte_cntr_data->pcie_chan_opened = true;
		mutex_unlock(&byte_cntr_data->byte_cntr_lock);
		}

		}

		static void etr_pcie_write_work_fn(struct work_struct *work)
		{
		int ret = 0;
		struct mhi_req *req;
		size_t actual;
		int bytes_to_write;
		char *buf;

		struct byte_cntr *byte_cntr_data = container_of(work,
		struct byte_cntr,
		pcie_write_work);

		while (tmcdrvdata->enable
		&& tmcdrvdata->out_mode == TMC_ETR_OUT_MODE_PCIE) {
		if (!atomic_read(&byte_cntr_data->irq_cnt)) {
		ret = wait_event_interruptible(
		byte_cntr_data->pcie_wait_wq,
		atomic_read(&byte_cntr_data->irq_cnt) > 0
		\|\| !tmcdrvdata->enable
		\|\| tmcdrvdata->out_mode != TMC_ETR_OUT_MODE_PCIE
		\|\| !byte_cntr_data->pcie_chan_opened);
		if (ret == -ERESTARTSYS \|\| !tmcdrvdata->enable
		\|\| tmcdrvdata->out_mode != TMC_ETR_OUT_MODE_PCIE
		\|\| !byte_cntr_data->pcie_chan_opened)
		break;
		}

		actual = PCIE_BLK_SIZE;
		buf = (char *)(tmcdrvdata->buf + byte_cntr_data->offset);
		req = kzalloc(sizeof(*req), GFP_KERNEL);
		if (!req)
		break;

		tmc_etr_read_bytes(byte_cntr_data, &byte_cntr_data->offset,
		PCIE_BLK_SIZE, &actual, &buf);

		if (actual <= 0) {
		kfree(req);
		req = NULL;
		break;
		}

		req->buf = buf;
		req->client = byte_cntr_data->out_handle;
		req->context = byte_cntr_data;
		req->len = actual;
		req->chan = byte_cntr_data->pcie_out_chan;
		req->mode = DMA_ASYNC;
		req->client_cb = etr_pcie_write_complete_cb;
		req->snd_cmpl = 1;

		bytes_to_write = mhi_dev_write_channel(req);
		if (bytes_to_write != PCIE_BLK_SIZE) {
		dev_err(tmcdrvdata->dev, "Write error %d\n",
		bytes_to_write);

		kfree(req);
		req = NULL;
		break;
		}

		mutex_lock(&byte_cntr_data->byte_cntr_lock);
		if (byte_cntr_data->offset + actual >= tmcdrvdata->size)
		byte_cntr_data->offset = 0;
		else
		byte_cntr_data->offset += actual;
		mutex_unlock(&byte_cntr_data->byte_cntr_lock);
		}
		}

		int etr_register_pcie_channel(struct byte_cntr *byte_cntr_data)
		{
		return mhi_register_state_cb(etr_pcie_client_cb, byte_cntr_data,
		byte_cntr_data->pcie_out_chan);
		}

		static int etr_pcie_init(struct byte_cntr *byte_cntr_data)
		{
		if (!byte_cntr_data)
		return -EIO;

		byte_cntr_data->pcie_out_chan = MHI_CLIENT_QDSS_IN;
		byte_cntr_data->offset = 0;
		byte_cntr_data->pcie_chan_opened = false;
		INIT_WORK(&byte_cntr_data->pcie_open_work, etr_pcie_open_work_fn);
		INIT_WORK(&byte_cntr_data->pcie_write_work, etr_pcie_write_work_fn);
		init_waitqueue_head(&byte_cntr_data->pcie_wait_wq);
		byte_cntr_data->pcie_wq = create_singlethread_workqueue("etr_pcie");
		if (!byte_cntr_data->pcie_wq)
		return -ENOMEM;

		return etr_register_pcie_channel(byte_cntr_data);
		}

		struct byte_cntr byte_cntr_init(struct amba_device adev,
		struct tmc_drvdata *drvdata)
		{
		@@ -399,6 +610,7 @@ struct byte_cntr byte_cntr_init(struct amba_device adev,
		init_waitqueue_head(&byte_cntr_data->wq);
		mutex_init(&byte_cntr_data->byte_cntr_lock);

		etr_pcie_init(byte_cntr_data);
		return byte_cntr_data;
		}
		EXPORT_SYMBOL(byte_cntr_init);

drivers/hwtracing/coresight/coresight-byte-cntr.h

+13 −0

Original line number	Diff line number	Diff line
		@@ -4,22 +4,35 @@
		#include <linux/amba/bus.h>
		#include <linux/wait.h>
		#include <linux/mutex.h>
		#include <linux/msm_mhi_dev.h>

		struct byte_cntr {
		struct cdev dev;
		struct class *driver_class;
		bool enable;
		bool read_active;
		bool pcie_chan_opened;
		uint32_t byte_cntr_value;
		uint32_t block_size;
		int byte_cntr_irq;
		atomic_t irq_cnt;
		wait_queue_head_t wq;
		wait_queue_head_t pcie_wait_wq;
		struct mutex byte_cntr_lock;
		struct coresight_csr *csr;
		u32 pcie_out_chan;
		struct mhi_dev_client *out_handle;
		struct work_struct pcie_open_work;
		struct work_struct pcie_write_work;
		struct workqueue_struct *pcie_wq;
		void (event_notifier)(struct mhi_dev_client_cb_reason cb);
		loff_t offset;
		};

		extern void tmc_etr_byte_cntr_start(struct byte_cntr *byte_cntr_data);
		extern void tmc_etr_byte_cntr_stop(struct byte_cntr *byte_cntr_data);
		extern int etr_register_pcie_channel(struct byte_cntr *byte_cntr_data);
		extern int etr_pcie_start(struct byte_cntr *byte_cntr_data);
		extern void etr_pcie_stop(struct byte_cntr *byte_cntr_data);

		#endif

drivers/hwtracing/coresight/coresight-tmc-etr.c

+28 −8

Original line number	Diff line number	Diff line
		@@ -873,7 +873,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
		if (!drvdata->vaddr) {
		spin_unlock_irqrestore(&drvdata->spinlock, flags);

		if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM) {
		if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM \|\|
		drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE) {
		/*
		* ETR DDR memory is not allocated until user enables
		* tmc at least once. If user specifies different ETR
		@@ -882,12 +883,18 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
		* enabling tmc; the new selection will be honored from
		* next tmc enable session.
		*/
		if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM) {
		if (drvdata->size != drvdata->mem_size) {
		tmc_etr_free_mem(drvdata);
		drvdata->size = drvdata->mem_size;
		drvdata->memtype = drvdata->mem_type;
		}

		} else {
		drvdata->memtype = TMC_ETR_MEM_TYPE_CONTIG;
		drvdata->size = TMC_ETR_PCIE_MEM_SIZE;
		}

		ret = tmc_etr_alloc_mem(drvdata);
		if (ret) {
		mutex_unlock(&drvdata->mem_lock);
		@@ -933,7 +940,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
		}

		drvdata->mode = CS_MODE_SYSFS;
		if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM)
		if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM \|\|
		drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE)
		tmc_etr_enable_hw(drvdata);

		drvdata->enable = true;
		@@ -946,6 +954,10 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)

		if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM)
		tmc_etr_byte_cntr_start(drvdata->byte_cntr);

		if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE)
		etr_pcie_start(drvdata->byte_cntr);

		mutex_unlock(&drvdata->mem_lock);

		if (!ret)
		@@ -1027,10 +1039,16 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev)

		spin_unlock_irqrestore(&drvdata->spinlock, flags);

		if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM) {
		if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM \|\|
		drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE) {
		if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE) {
		etr_pcie_stop(drvdata->byte_cntr);
		flush_workqueue(drvdata->byte_cntr->pcie_wq);
		} else
		tmc_etr_byte_cntr_stop(drvdata->byte_cntr);

		coresight_cti_unmap_trigin(drvdata->cti_reset, 2, 0);
		coresight_cti_unmap_trigout(drvdata->cti_flush, 3, 0);
		tmc_etr_byte_cntr_stop(drvdata->byte_cntr);
		tmc_etr_free_mem(drvdata);
		}
		out:
		@@ -1066,6 +1084,8 @@ int tmc_etr_switch_mode(struct tmc_drvdata drvdata, const char out_mode)
		new_mode = TMC_ETR_OUT_MODE_MEM;
		else if (!strcmp(out_mode, str_tmc_etr_out_mode[TMC_ETR_OUT_MODE_USB]))
		new_mode = TMC_ETR_OUT_MODE_USB;
		else if (!strcmp(out_mode, str_tmc_etr_out_mode[TMC_ETR_OUT_MODE_PCIE]))
		new_mode = TMC_ETR_OUT_MODE_PCIE;
		else
		return -EINVAL;

drivers/hwtracing/coresight/coresight-tmc.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -117,6 +117,8 @@
		#define TMC_ETR_BAM_PIPE_INDEX 0
		#define TMC_ETR_BAM_NR_PIPES 2

		#define TMC_ETR_PCIE_MEM_SIZE 0x400000

		enum tmc_config_type {
		TMC_CONFIG_TYPE_ETB,
		TMC_CONFIG_TYPE_ETR,
		@@ -167,12 +169,14 @@ enum tmc_etr_out_mode {
		TMC_ETR_OUT_MODE_NONE,
		TMC_ETR_OUT_MODE_MEM,
		TMC_ETR_OUT_MODE_USB,
		TMC_ETR_OUT_MODE_PCIE,
		};

		static const char * const str_tmc_etr_out_mode[] = {
		[TMC_ETR_OUT_MODE_NONE] = "none",
		[TMC_ETR_OUT_MODE_MEM] = "mem",
		[TMC_ETR_OUT_MODE_USB] = "usb",
		[TMC_ETR_OUT_MODE_PCIE] = "pcie",
		};

		struct tmc_etr_bam_data {