Merge branch 'for-4.17/libnvdimm' into libnvdimm-for-next (1ed41b56) · Commits · e / devices / android_kernel_xiaomi_nabu

Documentation/devicetree/bindings/pmem/pmem-region.txt

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		Device-tree bindings for persistent memory regions
		-----------------------------------------------------

		Persistent memory refers to a class of memory devices that are:

		a) Usable as main system memory (i.e. cacheable), and
		b) Retain their contents across power failure.

		Given b) it is best to think of persistent memory as a kind of memory mapped
		storage device. To ensure data integrity the operating system needs to manage
		persistent regions separately to the normal memory pool. To aid with that this
		binding provides a standardised interface for discovering where persistent
		memory regions exist inside the physical address space.

		Bindings for the region nodes:
		-----------------------------

		Required properties:
		- compatible = "pmem-region"

		- reg = <base, size>;
		The reg property should specificy an address range that is
		translatable to a system physical address range. This address
		range should be mappable as normal system memory would be
		(i.e cacheable).

		If the reg property contains multiple address ranges
		each address range will be treated as though it was specified
		in a separate device node. Having multiple address ranges in a
		node implies no special relationship between the two ranges.

		Optional properties:
		- Any relevant NUMA assocativity properties for the target platform.

		- volatile; This property indicates that this region is actually
		backed by non-persistent memory. This lets the OS know that it
		may skip the cache flushes required to ensure data is made
		persistent after a write.

		If this property is absent then the OS must assume that the region
		is backed by non-volatile memory.

		Examples:
		--------------------

		/*
		* This node specifies one 4KB region spanning from
		* 0x5000 to 0x5fff that is backed by non-volatile memory.
		*/
		pmem@5000 {
		compatible = "pmem-region";
		reg = <0x00005000 0x00001000>;
		};

		/*
		* This node specifies two 4KB regions that are backed by
		* volatile (normal) memory.
		*/
		pmem@6000 {
		compatible = "pmem-region";
		reg = < 0x00006000 0x00001000
		0x00008000 0x00001000 >;
		volatile;
		};

MAINTAINERS

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		@@ -8035,6 +8035,14 @@ Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
		S: Supported
		F: drivers/nvdimm/pmem*

		LIBNVDIMM: DEVICETREE BINDINGS
		M: Oliver O'Halloran <oohall@gmail.com>
		L: linux-nvdimm@lists.01.org
		Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
		S: Supported
		F: drivers/nvdimm/of_pmem.c
		F: Documentation/devicetree/bindings/pmem/pmem-region.txt

		LIBNVDIMM: NON-VOLATILE MEMORY DEVICE SUBSYSTEM
		M: Dan Williams <dan.j.williams@intel.com>
		L: linux-nvdimm@lists.01.org

arch/powerpc/platforms/powernv/opal.c

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		@@ -821,6 +821,9 @@ static int __init opal_init(void)
		/* Create i2c platform devices */
		opal_pdev_init("ibm,opal-i2c");

		/* Handle non-volatile memory devices */
		opal_pdev_init("pmem-region");

		/* Setup a heatbeat thread if requested by OPAL */
		opal_init_heartbeat();

drivers/acpi/nfit/core.c

+323 −356

File changed.

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drivers/acpi/nfit/mce.c

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		@@ -51,9 +51,8 @@ static int nfit_handle_mce(struct notifier_block *nb, unsigned long val,
		if ((spa->address + spa->length - 1) < mce->addr)
		continue;
		found_match = 1;
		dev_dbg(dev, "%s: addr in SPA %d (0x%llx, 0x%llx)\n",
		__func__, spa->range_index, spa->address,
		spa->length);
		dev_dbg(dev, "addr in SPA %d (0x%llx, 0x%llx)\n",
		spa->range_index, spa->address, spa->length);
		/*
		* We can break at the first match because we're going
		* to rescan all the SPA ranges. There shouldn't be any