Loading drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.c +16 −0 Original line number Diff line number Diff line Loading @@ -19,9 +19,14 @@ static int ufs_qcom_phy_qmp_v4_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, bool is_rate_B) { u8 major = ufs_qcom_phy->host_ctrl_rev_major; u16 minor = ufs_qcom_phy->host_ctrl_rev_minor; u16 step = ufs_qcom_phy->host_ctrl_rev_step; writel_relaxed(0x01, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET); /* Ensure PHY is in reset before writing PHY calibration data */ wmb(); /* * Writing PHY calibration in this order: * 1. Write Rate-A calibration first (1-lane mode). Loading @@ -37,6 +42,17 @@ int ufs_qcom_phy_qmp_v4_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B, ARRAY_SIZE(phy_cal_table_rate_B)); if ((major == 0x4) && (minor == 0x000) && (step == 0x0000)) { writel_relaxed(0x01, ufs_qcom_phy->mmio + QSERDES_RX0_AC_JTAG_ENABLE); writel_relaxed(0x01, ufs_qcom_phy->mmio + QSERDES_RX0_AC_JTAG_MODE); writel_relaxed(0x01, ufs_qcom_phy->mmio + QSERDES_RX1_AC_JTAG_ENABLE); writel_relaxed(0x01, ufs_qcom_phy->mmio + QSERDES_RX1_AC_JTAG_MODE); } writel_relaxed(0x00, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET); /* flush buffered writes */ wmb(); Loading drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h +0 −4 Original line number Diff line number Diff line Loading @@ -259,8 +259,6 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HS_GEAR_BAND, 0x06), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_ENABLE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_MODE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04), }; Loading Loading @@ -305,8 +303,6 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_ENABLE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_MODE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04), }; Loading Loading
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.c +16 −0 Original line number Diff line number Diff line Loading @@ -19,9 +19,14 @@ static int ufs_qcom_phy_qmp_v4_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, bool is_rate_B) { u8 major = ufs_qcom_phy->host_ctrl_rev_major; u16 minor = ufs_qcom_phy->host_ctrl_rev_minor; u16 step = ufs_qcom_phy->host_ctrl_rev_step; writel_relaxed(0x01, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET); /* Ensure PHY is in reset before writing PHY calibration data */ wmb(); /* * Writing PHY calibration in this order: * 1. Write Rate-A calibration first (1-lane mode). Loading @@ -37,6 +42,17 @@ int ufs_qcom_phy_qmp_v4_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B, ARRAY_SIZE(phy_cal_table_rate_B)); if ((major == 0x4) && (minor == 0x000) && (step == 0x0000)) { writel_relaxed(0x01, ufs_qcom_phy->mmio + QSERDES_RX0_AC_JTAG_ENABLE); writel_relaxed(0x01, ufs_qcom_phy->mmio + QSERDES_RX0_AC_JTAG_MODE); writel_relaxed(0x01, ufs_qcom_phy->mmio + QSERDES_RX1_AC_JTAG_ENABLE); writel_relaxed(0x01, ufs_qcom_phy->mmio + QSERDES_RX1_AC_JTAG_MODE); } writel_relaxed(0x00, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET); /* flush buffered writes */ wmb(); Loading
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h +0 −4 Original line number Diff line number Diff line Loading @@ -259,8 +259,6 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HS_GEAR_BAND, 0x06), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_ENABLE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_MODE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04), }; Loading Loading @@ -305,8 +303,6 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_ENABLE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_MODE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04), }; Loading