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Commit 1cf5f911 authored by Sunil Paidimarri's avatar Sunil Paidimarri Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add emac hw changes in sdmshrike 



Add emac hw node, interrupts and pins.

Change-Id: Ic4f6b7de704e39fce0afe011d0bce8ebf614cdee
Acked-by: default avatarNisha Menon <nmenon@qti.qualcomm.com>
Signed-off-by: default avatarSunil Paidimarri <hisunil@codeaurora.org>
parent a4a6b5b1

arch/arm64/boot/dts/qcom/sa8195p.dtsi

+88 −0
Original line number Diff line number Diff line
@@ -18,3 +18,91 @@ 
	qcom,msm-name = "SA8195P";

	qcom,msm-id = <405 0x20000>;

};



#include <dt-bindings/gpio/gpio.h>

&soc {

	emac_hw: qcom,emac@00020000 {

		compatible = "qcom,emac-dwc-eqos";

		qcom,arm-smmu;

		emac-core-version = <3>;

		reg = <0x20000 0x10000>,

			<0x36000 0x100>,

			<0x3D00000 0x300000>;

		reg-names = "emac-base", "rgmii-base", "tlmm-central-base";

		interrupts-extended = <&pdc 0 689 4>, <&pdc 0 700 4>,

			<&tlmm 124 2>, <&pdc 0 691 4>,

			<&pdc 0 692 4>, <&pdc 0 693 4>,

			<&pdc 0 694 4>, <&pdc 0 695 4>,

			<&pdc 0 696 4>, <&pdc 0 697 4>,

			<&pdc 0 698 4>, <&pdc 0 699 4>;

		interrupt-names = "sbd-intr", "lpi-intr",

			"phy-intr", "tx-ch0-intr",

			"tx-ch1-intr", "tx-ch2-intr",

			"tx-ch3-intr", "tx-ch4-intr",

			"rx-ch0-intr", "rx-ch1-intr",

			"rx-ch2-intr", "rx-ch3-intr";

		qcom,msm-bus,name = "emac";

		qcom,msm-bus,num-cases = <4>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

			<98 512 0 0>, <1 781 0 0>, /* No vote */

			<98 512 2500 0>, <1 781 0 40000>, /* 10Mbps vote */

			<98 512 25000 0>, <1 781 0 40000>, /* 100Mbps vote */

			<98 512 250000 0>, <1 781 0 40000>; /* 1000Mbps vote */

		qcom,bus-vector-names = "0", "10", "100", "1000";

		clocks = <&clock_gcc GCC_EMAC_AXI_CLK>,

			<&clock_gcc GCC_EMAC_PTP_CLK>,

			<&clock_gcc GCC_EMAC_RGMII_CLK>,

			<&clock_gcc GCC_EMAC_SLV_AHB_CLK>;

		clock-names = "emac_axi_clk", "emac_ptp_clk",

			"emac_rgmii_clk", "emac_slv_ahb_clk";

		qcom,phy-reset = <&tlmm 79 GPIO_ACTIVE_HIGH>;

		qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>;

		gdsc_emac-supply = <&emac_gdsc>;

		pinctrl-names = "dev-emac-mdc",

			"dev-emac-mdio",

			"dev-emac-rgmii_txd0_state",

			"dev-emac-rgmii_txd1_state",

			"dev-emac-rgmii_txd2_state",

			"dev-emac-rgmii_txd3_state",

			"dev-emac-rgmii_txc_state",

			"dev-emac-rgmii_tx_ctl_state",

			"dev-emac-rgmii_rxd0_state",

			"dev-emac-rgmii_rxd1_state",

			"dev-emac-rgmii_rxd2_state",

			"dev-emac-rgmii_rxd3_state",

			"dev-emac-rgmii_rxc_state",

			"dev-emac-rgmii_rx_ctl_state",

			"dev-emac-phy_intr",

			"dev-emac-phy_reset_state";



		pinctrl-0 = <&emac_mdc>;

		pinctrl-1 = <&emac_mdio>;



		pinctrl-2 = <&emac_rgmii_txd0>;

		pinctrl-3 = <&emac_rgmii_txd1>;

		pinctrl-4 = <&emac_rgmii_txd2>;

		pinctrl-5 = <&emac_rgmii_txd3>;

		pinctrl-6 = <&emac_rgmii_txc>;

		pinctrl-7 = <&emac_rgmii_tx_ctl>;



		pinctrl-8 = <&emac_rgmii_rxd0>;

		pinctrl-9 = <&emac_rgmii_rxd1>;

		pinctrl-10 = <&emac_rgmii_rxd2>;

		pinctrl-11 = <&emac_rgmii_rxd3>;

		pinctrl-12 = <&emac_rgmii_rxc>;

		pinctrl-13 = <&emac_rgmii_rx_ctl>;

		pinctrl-14 = <&emac_phy_intr>;

		pinctrl-15 = <&emac_phy_reset_state>;



		io-macro-info {

			io-macro-bypass-mode = <0>;

			io-interface = "rgmii";

		};

		emac_emb_smmu: emac_emb_smmu {

			compatible = "qcom,emac-smmu-embedded";

			iommus = <&apps_smmu 0x7C0 0x0>;

			qcom,iova-mapping = <0x80000000 0x40000000>;

		};

	};

};