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Commit 1cdadff1 authored by Krishna Manikandan's avatar Krishna Manikandan Committed by Gerrit - the friendly Code Review server
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drm/msm/sde: add qseed4 support 



Expose dynamic expansion flag in sde_drm_scaler_v2 structure,
add blend ratio HW programming for unsharp mask filters and
set default preload values based on scaler version.

Change-Id: I42804018dfe8cf08ef4d7e1e540fa01f4bdf5d0f
Signed-off-by: default avatarAlexander Beykun <abeykun@codeaurora.org>
Signed-off-by: default avatarKrishna Manikandan <mkrishn@codeaurora.org>
parent a2b0e7c7

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+4 −0
Original line number Diff line number Diff line
@@ -430,10 +430,14 @@ struct sde_src_blk { 
 * struct sde_scaler_blk: Scaler information

 * @info:   HW register and features supported by this sub-blk

 * @version: qseed block revision

 * @h_preload: horizontal preload

 * @v_preload: vertical preload

 */

struct sde_scaler_blk {

	SDE_HW_SUBBLK_INFO;

	u32 version;

	u32 h_preload;

	u32 v_preload;

};



struct sde_csc_blk {

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c

+3 −1
Original line number Diff line number Diff line
@@ -2543,7 +2543,8 @@ static int reg_dmav1_setup_scaler3_de(struct sde_reg_dma_setup_ops_cfg *buf, 


	de_config[1] = ((de_cfg->limit & 0xF) << 9) |

		((de_cfg->prec_shift & 0x7) << 13) |

		((de_cfg->clip & 0x7) << 16);

		((de_cfg->clip & 0x7) << 16) |

		((de_cfg->blend & 0xF) << 20);



	de_config[2] = (de_cfg->thr_quiet & 0xFF) |

		((de_cfg->thr_dieout & 0x3FF) << 16);
@@ -2631,6 +2632,7 @@ void reg_dmav1_setup_vig_qseed3(struct sde_hw_pipe *ctx, 


	op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;

	op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;

	op_mode |= (scaler3_cfg->dyn_exp_disabled) ? BIT(13) : 0;



	preload =

		((scaler3_cfg->preload_x[0] & 0x7F) << 0) |

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+2 −2
Original line number Diff line number Diff line
@@ -1327,8 +1327,8 @@ struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx, 
	_setup_layer_ops(hw_pipe, hw_pipe->cap->features);



	if (hw_pipe->ops.get_scaler_ver) {

		hw_pipe->cap->sblk->scaler_blk.version =

			hw_pipe->ops.get_scaler_ver(hw_pipe);

		sde_init_scaler_blk(&hw_pipe->cap->sblk->scaler_blk,

			hw_pipe->ops.get_scaler_ver(hw_pipe));

	}



	rc = sde_hw_blk_init(&hw_pipe->base, SDE_HW_BLK_SSPP, idx, &sde_hw_ops);

drivers/gpu/drm/msm/sde/sde_hw_util.c

+25 −11
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -63,6 +63,11 @@ static u32 sde_hw_util_log_mask = SDE_DBG_MASK_NONE; 
#define QSEED3L_COEF_LUT_SWAP_BIT          0

#define QSEED3L_DIR_FILTER_WEIGHT          0x60

#define QSEED3LITE_SCALER_VERSION          0x2004

#define QSEED4_SCALER_VERSION              0x3000



#define QSEED3_DEFAULT_PRELOAD_V 0x3

#define QSEED3_DEFAULT_PRELOAD_H 0x4

#define QSEED4_DEFAULT_PRELOAD_H 0x5



typedef void (*scaler_lut_type)(struct sde_hw_blk_reg_map *,

		struct sde_hw_scaler3_cfg *, u32);
@@ -89,6 +94,17 @@ u32 *sde_hw_util_get_log_mask_ptr(void) 
	return &sde_hw_util_log_mask;

}



void sde_init_scaler_blk(struct sde_scaler_blk *blk, u32 version)

{

	if (!blk)

		return;



	blk->version = version;

	blk->v_preload = QSEED3_DEFAULT_PRELOAD_V;

	blk->h_preload = QSEED4_DEFAULT_PRELOAD_H;

	if (version < QSEED4_SCALER_VERSION)

		blk->h_preload = QSEED3_DEFAULT_PRELOAD_H;

}

void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,

		const struct sde_drm_scaler_v2 *scale_v2)

{
@@ -125,7 +141,7 @@ void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg, 
	cfg->uv_sep_lut_idx = scale_v2->uv_sep_lut_idx;

	cfg->de.prec_shift = scale_v2->de.prec_shift;

	cfg->dir_weight = scale_v2->dir_weight;

	cfg->unsharp_mask_blend = scale_v2->unsharp_mask_blend;

	cfg->dyn_exp_disabled = (scale_v2->flags & SDE_DYN_EXP_DISABLE) ? 1 : 0;



	cfg->de.enable = scale_v2->de.enable;

	cfg->de.sharpen_level1 = scale_v2->de.sharpen_level1;
@@ -136,6 +152,7 @@ void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg, 
	cfg->de.thr_dieout = scale_v2->de.thr_dieout;

	cfg->de.thr_low = scale_v2->de.thr_low;

	cfg->de.thr_high = scale_v2->de.thr_high;

	cfg->de.blend = scale_v2->de_blend;



	for (i = 0; i < SDE_MAX_DE_CURVES; i++) {

		cfg->de.adjust_a[i] = scale_v2->de.adjust_a[i];
@@ -285,7 +302,8 @@ static void _sde_hw_setup_scaler3_de(struct sde_hw_blk_reg_map *c, 


	sharp_ctl = ((de_cfg->limit & 0xF) << 9) |

		((de_cfg->prec_shift & 0x7) << 13) |

		((de_cfg->clip & 0x7) << 16);

		((de_cfg->clip & 0x7) << 16) |

		((de_cfg->blend & 0xF) << 20);



	shape_ctl = (de_cfg->thr_quiet & 0xFF) |

		((de_cfg->thr_dieout & 0x3FF) << 16);
@@ -318,19 +336,14 @@ static void _sde_hw_setup_scaler3_de(struct sde_hw_blk_reg_map *c, 
static inline scaler_lut_type get_scaler_lut(

		struct sde_hw_scaler3_cfg *scaler3_cfg, u32 scaler_version)

{

	scaler_lut_type lut_ptr = NULL;

	scaler_lut_type lut_ptr = _sde_hw_setup_scaler3lite_lut;



	if (!(scaler3_cfg->lut_flag))

		return NULL;



	switch (scaler_version) {



	case QSEED3LITE_SCALER_VERSION:

		lut_ptr = _sde_hw_setup_scaler3lite_lut;

		break;

	default:

	if (scaler_version < QSEED3LITE_SCALER_VERSION)

		lut_ptr = _sde_hw_setup_scaler3_lut;

	}



	return lut_ptr;

}
@@ -355,6 +368,7 @@ void sde_hw_setup_scaler3(struct sde_hw_blk_reg_map *c, 


	op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;

	op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;

	op_mode |= (scaler3_cfg->dyn_exp_disabled) ? BIT(13) : 0;



	preload =

		((scaler3_cfg->preload_x[0] & 0x7F) << 0) |

drivers/gpu/drm/msm/sde/sde_hw_util.h

+7 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -55,6 +55,7 @@ struct sde_hw_blk_reg_map { 
 * @ adjust_a:      A-coefficients for mapping curve

 * @ adjust_b:      B-coefficients for mapping curve

 * @ adjust_c:      C-coefficients for mapping curve

 * @ blend:      Unsharp Blend Filter Ratio

 */

struct sde_hw_scaler3_de_cfg {

	u32 enable;
@@ -70,6 +71,7 @@ struct sde_hw_scaler3_de_cfg { 
	int16_t adjust_a[SDE_MAX_DE_CURVES];

	int16_t adjust_b[SDE_MAX_DE_CURVES];

	int16_t adjust_c[SDE_MAX_DE_CURVES];

	uint32_t blend;

};
@@ -108,7 +110,7 @@ struct sde_hw_scaler3_de_cfg { 
 * @ sep_lut:      pointer to separable filter LUT

 * @ de: detail enhancer configuration

 * @ dir_weight:   Directional Weight

 * @ unsharp_mask_blend:  Unsharp Blend Filter Ratio

 * @dyn_exp_disabled:     Dynamic expansion disabled

 */

struct sde_hw_scaler3_cfg {

	u32 enable;
@@ -150,7 +152,7 @@ struct sde_hw_scaler3_cfg { 
	 */

	struct sde_hw_scaler3_de_cfg de;

	uint32_t dir_weight;

	uint32_t unsharp_mask_blend;

	uint32_t dyn_exp_disabled;

};



struct sde_hw_scaler3_lut_cfg {
@@ -182,6 +184,8 @@ int sde_reg_read(struct sde_hw_blk_reg_map *c, u32 reg_off); 


void *sde_hw_util_get_dir(void);



void sde_init_scaler_blk(struct sde_scaler_blk *blk, u32 version);



void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,

		const struct sde_drm_scaler_v2 *scale_v2);